Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec

From	Patrice Chotard <patrice.chotard@st.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec
Date	2016-06-28 14:00 +0200
Message-ID	<rOZQl-6yo-17@gated-at.bofh.it> (permalink)
References	<rOXOy-593-29@gated-at.bofh.it> <rOXOy-593-31@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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Hi Russell

On 06/28/2016 11:49 AM, Russell King - ARM Linux wrote:
> On Tue, Jun 28, 2016 at 11:40:37AM +0200, patrice.chotard@st.com wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> This patch implements the write_sec callback that handle PL310
>> secure registers writes.
>> This callback is just a stub for now, to avoid system crash.
>> Later, it could handle SMC calls so that TZ handles the needed writes.
> Is there much point having the L2 cache DT node enabled if you have
> no support for the writes, which are required for the hardware to be
> enabled?
>
It's similar to what has been done for ux500 machine, in non secure 
mode, we
can't write in L2 cache secure registers.

Patrice

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[PATCH] ARM: sti: Implement dummy L2 cache's write_sec <patrice.chotard@st.com> - 2016-06-28 11:50 +0200
  Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec Russell King - ARM Linux <linux@armlinux.org.uk> - 2016-06-28 11:50 +0200
    Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec Patrice Chotard <patrice.chotard@st.com> - 2016-06-28 14:00 +0200

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