[PATCH] ARM: sti: Implement dummy L2 cache's write_sec

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From	<patrice.chotard@st.com>
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Subject	[PATCH] ARM: sti: Implement dummy L2 cache's write_sec
Date	Tue, 28 Jun 2016 11:50:02 +0200
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From: Patrice Chotard <patrice.chotard@st.com>

This patch implements the write_sec callback that handle PL310
secure registers writes.
This callback is just a stub for now, to avoid system crash.
Later, it could handle SMC calls so that TZ handles the needed writes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 arch/arm/mach-sti/board-dt.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index cfee0ef..e04cd1b 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -23,6 +23,14 @@ static const char *const stih41x_dt_match[] __initconst = {
 	NULL
 };
 
+static void sti_l2_write_sec(unsigned long val, unsigned reg)
+{
+	/*
+	 * We can't write to secure registers as we are in non-secure
+	 * mode, until we have some SMI service available.
+	 */
+}
+
 DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
 	.dt_compat	= stih41x_dt_match,
 	.l2c_aux_val	= L2C_AUX_CTRL_SHARED_OVERRIDE |
@@ -31,4 +39,5 @@ DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
 			  L2C_AUX_CTRL_WAY_SIZE(4),
 	.l2c_aux_mask	= 0xc0000fff,
 	.smp		= smp_ops(sti_smp_ops),
+	.l2c_write_sec	= sti_l2_write_sec,
 MACHINE_END
-- 
1.9.1

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[PATCH] ARM: sti: Implement dummy L2 cache's write_sec <patrice.chotard@st.com> - 2016-06-28 11:50 +0200
  Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec Russell King - ARM Linux <linux@armlinux.org.uk> - 2016-06-28 11:50 +0200
    Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec Patrice Chotard <patrice.chotard@st.com> - 2016-06-28 14:00 +0200

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