[PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register

From	Andrey Smirnov <andrew.smirnov@gmail.com>
Newsgroups	linux.kernel
Subject	[PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register
Date	2016-06-19 02:40 +0200
Message-ID	<rLyWl-2XM-19@gated-at.bofh.it> (permalink)
References	<rLyWl-2XM-5@gated-at.bofh.it>
Organization	linux.* mail to news gateway

Show all headers | View raw

As per L2C-310 TRM[1]:

"... You can control this feature using bits 30,27 and 23 of the
Prefetch Control Register. Bit 23 and 27 are only used if you set bit 30
HIGH..."

which means there is no need to clear bit 23 if bit 30 is being cleared.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246e/CJAJACBJ.html

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mm/cache-l2x0.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 30e2012..12c1ba7 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -715,11 +715,8 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
 	if (revision >= L310_CACHE_ID_RTL_R3P0 &&
 	    revision < L310_CACHE_ID_RTL_R3P2) {
 		u32 val = l2x0_saved_regs.prefetch_ctrl;
-		/* I don't think bit23 is required here... but iMX6 does so */
-		if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL |
-			   L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) {
-			val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL |
-				 L310_PREFETCH_CTRL_DBL_LINEFILL_INCR);
+		if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) {
+			val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
 			l2x0_saved_regs.prefetch_ctrl = val;
 			errata[n++] = "752271";
 		}
-- 
2.5.5

Thread

[PATCH v3 0/5] i.MX L2-cache code cleanups and performance tweaks Andrey Smirnov <andrew.smirnov@gmail.com> - 2016-06-19 02:40 +0200
  [PATCH v3 2/5] i.MX: system.c: Remove redundant errata 752271 code Andrey Smirnov <andrew.smirnov@gmail.com> - 2016-06-19 02:40 +0200
  [PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Andrey Smirnov <andrew.smirnov@gmail.com> - 2016-06-19 02:40 +0200
  [PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register Andrey Smirnov <andrew.smirnov@gmail.com> - 2016-06-19 02:40 +0200
  Re: [PATCH v3 0/5] i.MX L2-cache code cleanups and performance tweaks Andrey Smirnov <andrew.smirnov@gmail.com> - 2016-06-19 03:10 +0200
  Re: [PATCH v3 0/5] i.MX L2-cache code cleanups and performance tweaks Arnd Bergmann <arnd@arndb.de> - 2016-06-19 16:50 +0200
    Re: [PATCH v3 0/5] i.MX L2-cache code cleanups and performance tweaks Andrey Smirnov <andrew.smirnov@gmail.com> - 2016-06-19 20:00 +0200
      Re: [PATCH v3 0/5] i.MX L2-cache code cleanups and performance tweaks Arnd Bergmann <arnd@arndb.de> - 2016-06-21 01:50 +0200

csiph-web