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Re: [PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs

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Am Montag, 13. Juni 2016, 16:04:27 schrieb Douglas Anderson:
> As can be seen in Arasan's datasheet [1] there are several "corecfg"
> settings in their SDHCI IP Block that are supposed to be controlled by
> software.  Although the datasheet referenced is a bit vague about how to
> access corecfg, in Figure 5 you can see that for Arasan's PHY (a
> separate component than their SDHCI component) they describe the
> "phyctrl" registers as being "FROM SOC CTL REG", implying that it's up
> to the licensee of the Arasan IP block to implement these registers.  It
> seems sane to assume that the "corecfg" registers in their SDHCI IP
> block works in a similar way for all licensees of the IP Block.
> 
> Device tree has a model that allows a device to get a reference to
> random registers located elsewhere in the SoC: sysctl.  Let's leverage
> this model and allow adding a sysctl reference to access the control
> registers for the Arasan SDHCI PHYs.
> 
> Having a reference to the control registers doesn't do much for us on
> its own since the Arasan spec doesn't specify how these corecfg values
> are laid out in memory.  In the SDHCI driver we'll need a map detailing
> where each corecfg can be found in each implementation.  This map can be
> found using the primary compatible string of the SDHCI device.  In that
> spirit, document that existing rk3399 device trees already have a
> specific compatible string, though up to now they've always been relying
> on the driver supporting the generic.
> 
> Note that since existing devices seem to work fairly well as-is, we'll
> list the syscon reference as "optional", but it's likely that we'll run
> into much fewer problems if we can actually set the proper values in the
> syscon, so it is strongly suggested that any SoCs where we have a map to
> set the corecfg also include a reference to the syscon.
> 
> [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
> 
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Acked-by: Rob Herring <robh@kernel.org>

I was trying to find public datasheets of other arasan-5.1 users, but wasn't 
sucessful. But I guess this solution should be versatile enough to support the 
implementation on other socs anyway, so

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

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[PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:10 +0200
  [PATCH v2 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:10 +0200
    Re: [PATCH v2 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Heiko Stübner <heiko@sntech.de> - 2016-06-18 14:10 +0200
  [PATCH v2 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:10 +0200
    Re: [PATCH v2 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Heiko Stuebner <heiko@sntech.de> - 2016-06-18 20:10 +0200
  [PATCH v2 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:10 +0200
    Re: [PATCH v2 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Doug Anderson <dianders@chromium.org> - 2016-06-15 18:50 +0200
  [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:10 +0200
    Re: [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY  get an exported card clock Rob Herring <robh@kernel.org> - 2016-06-16 20:50 +0200
    Re: [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Heiko Stübner <heiko@sntech.de> - 2016-06-18 23:50 +0200
    Re: [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY  get an exported card clock Kishon Vijay Abraham I <kishon@ti.com> - 2016-06-20 15:10 +0200
  [PATCH v2 09/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_on/off() Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:10 +0200
    Re: [PATCH v2 09/11] phy: rockchip-emmc: Minor code cleanup in  rockchip_emmc_phy_power_on/off() Shawn Lin <shawn.lin@rock-chips.com> - 2016-06-14 02:40 +0200
  [PATCH v2 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:10 +0200
    Re: [PATCH v2 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Heiko Stuebner <heiko@sntech.de> - 2016-06-18 20:10 +0200
  [PATCH v2 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:20 +0200
    Re: [PATCH v2 01/11] phy: rockchip-emmc: Increase lock time allowance Shawn Lin <shawn.lin@rock-chips.com> - 2016-06-14 02:30 +0200
  [PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson <dianders@chromium.org> - 2016-06-14 01:20 +0200
    Re: [PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add  soc-ctl-syscon for corecfg regs Shawn Lin <shawn.lin@rock-chips.com> - 2016-06-14 02:40 +0200
    Re: [PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Heiko Stübner <heiko@sntech.de> - 2016-06-18 16:20 +0200
  Re: [PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399 Heiko Stuebner <heiko@sntech.de> - 2016-06-17 01:50 +0200
  Re: [PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399 Kishon Vijay Abraham I <kishon@ti.com> - 2016-06-17 14:50 +0200
    Re: [PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399 Doug Anderson <dianders@chromium.org> - 2016-06-17 17:40 +0200

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