Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1412965
| From | Peter Zijlstra <peterz@infradead.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX |
| Date | 2016-06-03 11:30 +0200 |
| Message-ID | <rFTAt-1l9-7@gated-at.bofh.it> (permalink) |
| References | <rFqRP-8y-5@gated-at.bofh.it> <rFqRP-8y-3@gated-at.bofh.it> <rFwDU-3I1-17@gated-at.bofh.it> <rFTAt-1l9-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Thu, Jun 02, 2016 at 05:00:19PM +0000, David Carrillo-Cisneros wrote: > LBR_FROM_FLAG_MISPRED is at bit 63 so the bitshift wouldnt work . But I can > clean the bits unconditionally of the value, just as you said for the read > case. Argh, missed that. Ok, something like so then: #define LBR_FROM_SIGN_MASK (BIT_ULL(61) | BIT_ULL(62)) /* * Sign extend into bits 61,62 while preserving bit 63. * * This works because bits 59 and 60 are guaranteed to be sign * bits themselves. */ val = (val & ~LBR_FROM_SIGN_MASK) | ((val << 2) & LBR_FROM_SIGN_MASK); A superscalar core can evaluate the left and right hand parts of the logical or concurrently. I've not generated the code so see what GCC does with the 64bit literals, ideally it would generate code using 32bit literals and only operate on the high word, but who knows if its smart enough for that. See also: https://graphics.stanford.edu/~seander/bithacks.html#ConditionalSetOrClearBitsWithoutBranching
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX David Carrillo-Cisneros <davidcc@google.com> - 2016-06-02 04:50 +0200
Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX Peter Zijlstra <peterz@infradead.org> - 2016-06-02 10:30 +0200
Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX Peter Zijlstra <peterz@infradead.org> - 2016-06-02 10:40 +0200
Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX Peter Zijlstra <peterz@infradead.org> - 2016-06-02 11:00 +0200
Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX Peter Zijlstra <peterz@infradead.org> - 2016-06-02 11:00 +0200
Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX Peter Zijlstra <peterz@infradead.org> - 2016-06-03 11:30 +0200
Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX Peter Zijlstra <peterz@infradead.org> - 2016-06-02 11:00 +0200
Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX Andi Kleen <ak@linux.intel.com> - 2016-06-02 18:10 +0200
csiph-web