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Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to proper values

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On Thu, Jun 02, 2016 at 11:35:40AM -0700, Stephen Boyd wrote:
> On 06/02, Banavathi, Pradeep wrote:
> > The PLLs on IPQ4019 cannot be reconfigured by design. The
> > recommendation is to program these PLLS only once. Since, the
> > Bootloaders configure the PLLs and clocks already. we did not
> > support the recalc rate and marked them as fixed clocks.
> > 
> 
> (Please don't top post)
> 
> That doesn't matter. We recalculate PLL rates on all other qcom
> SoCs by reading the hardware even though an overwhelming majority
> of them are fixed by the bootloader.
>
We will check for this. Already we added the APSS CPU PLL divider
in clock framework in next 3 patches of this patchset. Could you
please review the same so that we can follow the similar thing for
other PLL and dividers.
> -- 
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

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Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to  proper values Stephen Boyd <sboyd@codeaurora.org> - 2016-06-02 00:20 +0200
  Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to  proper values "Banavathi, Pradeep" <pradeepb@codeaurora.org> - 2016-06-02 16:20 +0200
    Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to  proper values Stephen Boyd <sboyd@codeaurora.org> - 2016-06-02 20:40 +0200
      Re: [PATCH 1/5] clk: qcom: ipq4019: Modified the fixed clock rate to  proper values Abhishek Sahu <absahu@codeaurora.org> - 2016-06-02 21:20 +0200

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