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[PATCH 11/17] pinctrl: uniphier: support per-pin input enable for new SoCs

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Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin.  (While, existing ones only support it
per pin-group.)  This commit updates the core part for that.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 24 +++++++++++++-----------
 drivers/pinctrl/uniphier/pinctrl-uniphier.h      |  1 +
 2 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index ca2562a..d774a8e 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -433,22 +433,24 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
 {
 	struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 	unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
+	unsigned int reg, mask;
 
-	if (enable == 0) {
-		/*
-		 * Multiple pins share one input enable, so per-pin disabling
-		 * is impossible.
-		 */
-		dev_err(pctldev->dev, "unable to disable input\n");
+	/*
+	 * Multiple pins share one input enable, per-pin disabling is
+	 * impossible.
+	 */
+	if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) &&
+	    !enable)
 		return -EINVAL;
-	}
 
+	/* UNIPHIER_PIN_IECTRL_NONE means the pin is always input-enabled */
 	if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
-		/* This pin is always input-enabled. nothing to do. */
-		return 0;
+		return enable ? 0 : -EINVAL;
+
+	reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
+	mask = BIT(iectrl % 32);
 
-	return regmap_update_bits(priv->regmap, UNIPHIER_PINCTRL_IECTRL,
-				  BIT(iectrl), BIT(iectrl));
+	return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);
 }
 
 static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 3fd5020..9941a4c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -166,6 +166,7 @@ struct uniphier_pinctrl_socdata {
 	const struct uniphier_pinmux_function *functions;
 	int functions_count;
 	unsigned int caps;
+#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL	BIT(1)
 #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE	BIT(0)
 };
 
-- 
1.9.1

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Thread

[PATCH 00/17] pinctrl: uniphier: many clean-ups and support new pinctrl drivers Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-31 10:20 +0200
  [PATCH 14/17] pinctrl: uniphier: add System Bus pin-mux settings Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-31 10:20 +0200
  [PATCH 06/17] pinctrl: uniphier: allocate struct pinctrl_desc in probe function Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-31 10:20 +0200
  [PATCH 03/17] pinctrl: uniphier: fix register offsets for drive strength control Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-31 10:20 +0200
    Re: [PATCH 03/17] pinctrl: uniphier: fix register offsets for drive  strength control Linus Walleij <linus.walleij@linaro.org> - 2016-05-31 12:40 +0200
  [PATCH 02/17] pinctrl: uniphier: rename function and variable names Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-31 10:20 +0200
  [PATCH 08/17] pinctrl: uniphier: support 3-bit drive strength control Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-31 10:20 +0200
  [PATCH 11/17] pinctrl: uniphier: support per-pin input enable for new SoCs Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-31 10:20 +0200

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