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Groups > linux.kernel > #1405839
| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 |
| Date | 2016-05-24 07:10 +0200 |
| Message-ID | <rCcLn-7ot-9@gated-at.bofh.it> (permalink) |
| References | <rCcLn-7ot-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").
The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 337912b..88d56ad 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -163,8 +163,8 @@
#define HSYNC_POLARITY_CFG (0x1 << 0)
/* ANALOGIX_DP_PLL_REG_1 */
-#define REF_CLK_24M (0x1 << 1)
-#define REF_CLK_27M (0x0 << 1)
+#define REF_CLK_24M (0x1 << 0)
+#define REF_CLK_27M (0x0 << 0)
/* ANALOGIX_DP_LANE_MAP */
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
--
1.9.1
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[PATCH v2 0/10] Add RK3399 eDP support and fix some bugs to analogix_dp driver. Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
[PATCH v2 09/10] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
[PATCH v2 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
[PATCH v2 06/10] drm/rockchip: analogix_dp: make panel detect to an optional action Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
[PATCH v2 02/10] drm/rockchip: analogix_dp: split the lcdc select setting into device data Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
[PATCH v2 08/10] drm/rockchip: analogix_dp: correct the connector display color format and bpc Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
[PATCH v2 04/10] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
[PATCH v2 07/10] drm/bridge: analogix_dp: introduce connector mode_valid callback to plat driver Yakir Yang <ykk@rock-chips.com> - 2016-05-24 07:10 +0200
Re: [PATCH v2 0/10] Add RK3399 eDP support and fix some bugs to analogix_dp driver. Yakir Yang <ykk@rock-chips.com> - 2016-05-26 11:40 +0200
Re: [PATCH v2 0/10] Add RK3399 eDP support and fix some bugs to analogix_dp driver. Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-26 14:50 +0200
Re: [PATCH v2 0/10] Add RK3399 eDP support and fix some bugs to analogix_dp driver. Yakir Yang <ykk@rock-chips.com> - 2016-05-27 08:20 +0200
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