Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1347953
| From | Borislav Petkov <bp@alien8.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors |
| Date | 2016-03-02 12:00 +0100 |
| Message-ID | <r8cFA-6tO-9@gated-at.bofh.it> (permalink) |
| References | <r7Ekx-tv-7@gated-at.bofh.it> <r7Eky-tv-17@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Mon, Feb 29, 2016 at 04:32:56PM -0600, Aravind Gopalakrishnan wrote:
> For Scalable MCA enabled processors, errors are listed
> per IP block. And since it is not required for an IP to
> map to a particular bank, we need to use HWID and McaType
> values from the MCx_IPID register to figure out which IP
> a given bank represents.
>
> We also have a new bit (TCC) in the MCx_STATUS register
> to indicate Task context is corrupt.
>
> Add logic here to decode errors from all known IP
> blocks for Fam17h Model 00-0fh and to print TCC errors.
>
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
> ---
> arch/x86/include/asm/mce.h | 53 ++++++
> arch/x86/kernel/cpu/mcheck/mce_amd.c | 11 ++
> drivers/edac/mce_amd.c | 342 ++++++++++++++++++++++++++++++++++-
> 3 files changed, 405 insertions(+), 1 deletion(-)
Ok, applied with a bunch of changes ontop. I'm sending them as a reply
to this message. The second patch is relying on the assumption that a
hwid of 0 is invalid. Is that so?
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH V2 0/5] Updates to EDAC and AMD MCE driver Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-02-29 23:20 +0100
[PATCH V2 3/5] x86/mce/AMD: Fix logic to obtain block address Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-02-29 23:20 +0100
[PATCH V2 1/5] x86/mce: Move MCx_CONFIG MSR definition Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-02-29 23:20 +0100
[PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-02-29 23:20 +0100
[PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding Borislav Petkov <bp@alien8.de> - 2016-03-02 12:00 +0100
Re: [PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding Borislav Petkov <bp@alien8.de> - 2016-03-02 17:30 +0100
Re: [PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding Borislav Petkov <bp@alien8.de> - 2016-03-02 17:40 +0100
Re: [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors Borislav Petkov <bp@alien8.de> - 2016-03-02 12:00 +0100
[PATCH 3/3] EDAC, mce_amd: Correct error paths Borislav Petkov <bp@alien8.de> - 2016-03-02 12:00 +0100
[PATCH 1/3] x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors Borislav Petkov <bp@alien8.de> - 2016-03-02 12:00 +0100
csiph-web