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Re: [PATCH v4 3/5] arm64: dts: Add Cavium ThunderX specific PMU

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On 02/18/2016 09:32 AM, Will Deacon wrote:
> On Thu, Feb 18, 2016 at 05:50:12PM +0100, Jan Glauber wrote:
>> Add a compatible string for the Cavium ThunderX PMU.
>
> Stupid question, but is "thunder" the name of the CPU or the SoC or ...?

At a high level Cavium ThunderX (tm) is a family of SoCs.  Since the SoC 
contains many different functional blocks ...

>
> Whatever we use to describe the PMU, should probably also identify the
> CPU uniquely.

... In the context of this patch, "cavium,thunder-pmu" refers to the PMU 
of Cavium's implementation of the ARMv8 Processing Element (PE) 
specification (i.e. the CPU), as found on the CN88XX family of SoCs.

If we think of this in terms of MIDR_EL1, That would be:

    Implementer: 0x43
    PartNum: 0xA1


>
> Will
>
>> Signed-off-by: Jan Glauber <jglauber@cavium.com>
>> ---
>>   Documentation/devicetree/bindings/arm/pmu.txt | 1 +
>>   arch/arm64/boot/dts/cavium/thunder-88xx.dtsi  | 5 +++++
>>   2 files changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
>> index 5651883..d3999a1 100644
>> --- a/Documentation/devicetree/bindings/arm/pmu.txt
>> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
>> @@ -25,6 +25,7 @@ Required properties:
>>   	"qcom,scorpion-pmu"
>>   	"qcom,scorpion-mp-pmu"
>>   	"qcom,krait-pmu"
>> +	"cavium,thunder-pmu"
>>   - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
>>                  interrupt (PPI) then 1 interrupt should be specified.
>>
>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
>> index 9cb7cf9..2eb9b22 100644
>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
>> @@ -360,6 +360,11 @@
>>   		             <1 10 0xff01>;
>>   	};
>>
>> +	pmu {
>> +		compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
>> +		interrupts = <1 7 4>;
>> +	};
>> +
>>   	soc {
>>   		compatible = "simple-bus";
>>   		#address-cells = <2>;
>> --
>> 1.9.1
>>
>
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>

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Thread

[PATCH v4 0/5] Cavium ThunderX PMU support Jan Glauber <jglauber@cavium.com> - 2016-02-18 18:00 +0100
  [PATCH v4 3/5] arm64: dts: Add Cavium ThunderX specific PMU Jan Glauber <jglauber@cavium.com> - 2016-02-18 18:00 +0100
    Re: [PATCH v4 3/5] arm64: dts: Add Cavium ThunderX specific PMU Will Deacon <will.deacon@arm.com> - 2016-02-18 18:40 +0100
      Re: [PATCH v4 3/5] arm64: dts: Add Cavium ThunderX specific PMU David Daney <ddaney@caviumnetworks.com> - 2016-02-18 19:40 +0100
      Re: [PATCH v4 3/5] arm64: dts: Add Cavium ThunderX specific PMU Jan Glauber <jan.glauber@caviumnetworks.com> - 2016-02-22 13:50 +0100
  [PATCH v4 1/5] arm64/perf: Rename Cortex A57 events Jan Glauber <jglauber@cavium.com> - 2016-02-18 18:00 +0100

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