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Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit

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On Thu, Feb 18, 2016 at 05:50:13PM +0100, Jan Glauber wrote:
> With the long cycle counter bit (LC) disabled the cycle counter is not
> working on ThunderX SOC (ThunderX only implements Aarch64).
> Also, according to documentation LC == 0 is deprecated.
> 
> To keep the code simple the patch does not introduce 64 bit wide counter
> functions. Instead writing the cycle counter always sets the upper
> 32 bits so overflow interrupts are generated as before.
> 
> Original patch from Andrew Pinksi <Andrew.Pinksi@caviumnetworks.com>

What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?

Will

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[PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit Jan Glauber <jglauber@cavium.com> - 2016-02-18 18:00 +0100
  Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit Will Deacon <will.deacon@arm.com> - 2016-02-18 18:40 +0100
    Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit Jan Glauber <jan.glauber@caviumnetworks.com> - 2016-02-18 19:30 +0100
    Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit David Daney <ddaney@caviumnetworks.com> - 2016-02-18 20:00 +0100
    Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit Jan Glauber <jan.glauber@caviumnetworks.com> - 2016-02-22 13:50 +0100
      Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit Will Deacon <will.deacon@arm.com> - 2016-02-22 14:50 +0100

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