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Groups > linux.kernel > #1275970
| From | "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 5/5] arm64: Ensure the secondary CPUs have safe ASIDBits size |
| Date | 2015-11-24 00:50 +0100 |
| Message-ID | <qy91T-dn-7@gated-at.bofh.it> (permalink) |
| References | <qwep4-5SC-3@gated-at.bofh.it> <qwep4-5SC-5@gated-at.bofh.it> <qwep5-5SC-31@gated-at.bofh.it> <qy36a-4UC-21@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 23/11/15 17:29, Will Deacon wrote:
> On Wed, Nov 18, 2015 at 05:09:00PM +0000, Suzuki K. Poulose wrote:
>> The ID_AA64MMFR0_EL1:ASIDBits determines the size of the mm context
>> id and is used in the early boot to make decisions. The value is
>> picked up from the Boot CPU and cannot be delayed until other CPUs
>> are up. If a secondary CPU has a smaller size than that of the Boot
>> CPU, things will break horribly and the usual SANITY check is not good
>> enough to prevent the system from crashing. Prevent this by failing CPUs with
>> ASID smaller than that of the boot CPU.
...
>> + pr_crit("CPU%d: will not boot\n", cpu);
>
> This is less informative than the current message (whcih describes the
> missing capability).
The missing capability is printed by the caller (Patch 4/5) and see below
for the new user.
ID_AA64MMFR0_ASID_SHIFT);
>> + if (asid_cur < asid_boot) {
>> + pr_crit("CPU%d: has incompatible ASIDBits: %u vs Boot CPU:%u\n",
>> + cpu, asid_cur, asid_boot);
>> + fail_incapable_cpu();
>> + }
>
> Hmm. Whilst we want to ensure that secondary CPUs don't have a smaller
> ASID size than the boot CPU, can we actually guarantee that a smaller
> value for ID_AA64MMFR0.ASIDBits corresponds to fewer bits? We're
> probably better off assuming 8-bit ASIDs unless ASIDBits == 2 (which is
> what the ASID allocator does).
Right, I already have a reworked version, which does the same and moves it
back to verify_local_cpu_capabilities(). I will send it tomorrow.
Cheers
Suzuki
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[PATCH 0/5] arm64: cpufeature: Fixes for 4.4-rc1 "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-11-18 18:10 +0100
[PATCH 1/5] arm64: cpufeature: Add helpers for extracting unsigned values "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-11-18 18:10 +0100
[PATCH 4/5] arm64: Make fail_incapable_cpu reusable "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-11-18 18:10 +0100
[PATCH 2/5] arm64: cpufeature: Track unsigned fields "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-11-18 18:10 +0100
Re: [PATCH 2/5] arm64: cpufeature: Track unsigned fields AKASHI Takahiro <takahiro.akashi@linaro.org> - 2015-11-19 06:00 +0100
Re: [PATCH 2/5] arm64: cpufeature: Track unsigned fields "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> - 2015-11-19 11:10 +0100
Re: [PATCH 2/5] arm64: cpufeature: Track unsigned fields "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> - 2015-11-19 11:10 +0100
Re: [PATCH 2/5] arm64: cpufeature: Track unsigned fields Catalin Marinas <catalin.marinas@arm.com> - 2015-11-19 19:50 +0100
Re: [PATCH 2/5] arm64: cpufeature: Track unsigned fields "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> - 2015-11-20 14:40 +0100
[PATCH 5/5] arm64: Ensure the secondary CPUs have safe ASIDBits size "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-11-18 18:10 +0100
Re: [PATCH 5/5] arm64: Ensure the secondary CPUs have safe ASIDBits size Will Deacon <will.deacon@arm.com> - 2015-11-23 18:30 +0100
Re: [PATCH 5/5] arm64: Ensure the secondary CPUs have safe ASIDBits size "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> - 2015-11-24 00:50 +0100
[PATCH 3/5] arm64: debug: Treat the BRPs/WRPs as unsigned "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-11-18 18:20 +0100
Re: [PATCH 3/5] arm64: debug: Treat the BRPs/WRPs as unsigned Will Deacon <will.deacon@arm.com> - 2015-11-23 18:40 +0100
Re: [PATCH 0/5] arm64: cpufeature: Fixes for 4.4-rc1 Catalin Marinas <catalin.marinas@arm.com> - 2015-11-26 19:20 +0100
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