Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

From	Peter Zijlstra <peterz@infradead.org>
Newsgroups	linux.kernel
Subject	Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error
Date	2015-11-13 21:50 +0100
Message-ID	<qutse-2O8-5@gated-at.bofh.it> (permalink)
References	(2 earlier) <qtlQ6-9M-31@gated-at.bofh.it> <qtlQ6-9M-29@gated-at.bofh.it> <qtn5w-Uo-25@gated-at.bofh.it> <qto1A-1vO-13@gated-at.bofh.it> <qtFYu-4IH-1@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote:
> I also wrote a small C utility[1], with a bit of code borrowed from the
> kernel, for reading the TSC on all CPUs. It starts a high priority
> thread per CPU, tries to synchronize them and prints out the TSC values
> and their offset with regards to CPU0.
> It can be called from a SysV init shell script[2] at the beginning of
> the boot process and right before a reboot to save the values in a file.

Could you also read and print TSC_ADJUST (msr 0x3b) ? This would tell us
if for example your BIOS messed it up.

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Thread

[RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error gratian.crisan@ni.com - 2015-11-09 21:10 +0100
  Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs  with offset error Peter Zijlstra <peterz@infradead.org> - 2015-11-09 23:10 +0100
    Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs  with offset error Josh Hunt <joshhunt00@gmail.com> - 2015-11-10 19:30 +0100
      Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error Gratian Crisan <gratian.crisan@ni.com> - 2015-11-10 20:50 +0100
        Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs  with offset error Josh Hunt <joshhunt00@gmail.com> - 2015-11-10 21:50 +0100
          Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error Gratian Crisan <gratian.crisan@ni.com> - 2015-11-11 17:00 +0100
            Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs  with offset error Peter Zijlstra <peterz@infradead.org> - 2015-11-13 21:50 +0100
    Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs  with offset error Dave Hansen <dave.hansen@intel.com> - 2015-11-13 22:20 +0100

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