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Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges

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Hi Gerry,

On 16/10/15 02:55, Jiang Liu wrote:
> On 2015/10/15 23:39, Marc Zyngier wrote:
>> There seems to be a new class of interrupt controller out there whose
>> sole purpose (apart from making everybody's life a nightmare) is to
>> turn wired interrupts into MSIs.
>>
>> Instead of considering that the MSIs allocated to a device are for the
>> direct use of that device, we can turn this set of MSIs into a irq
>> domain, and use that domain to build a standard irqchip on top of
>> that.
> Hi Marc,
> 	There's a working to enable Intel VMD storage device, which
> has the similar requirement. Basically a PCIe hierarchy is hidden
> behind a parent PCIe device, so we need to use the PCIe irqs on parent
> to de-multiple PCIe IRQs from hidden PCIe devices. Seems a chance for
> consolidation here.

Do you know if there is a 1-1 mapping between the interrupts seen by the
parent device and those seen by the hidden devices? Or is it a case of
having to demultiplex the MSIs? Looks like the former, but I'd like to
be sure.

I just had a quick look at the code there:
https://lkml.org/lkml/2015/8/27/674

Is there anything more recent?

> 	cc Keith Busch <keith.busch@intel.com> who is the author of
> VMD device driver.

Sure, will do when I repost this (probably in a few weeks), and assuming
this fits the bill for Thomas and the MBIGEN folks.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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[PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  [PATCH RFC 2/7] platform-msi: Factor out allocation/free of private data Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
    Re: [PATCH RFC 2/7] platform-msi: Factor out allocation/free of  private data Jiang Liu <jiang.liu@linux.intel.com> - 2015-10-16 07:50 +0200
      Re: [PATCH RFC 2/7] platform-msi: Factor out allocation/free of private  data Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 11:00 +0200
  [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
    RE: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Gabriele Paoloni <gabriele.paoloni@huawei.com> - 2015-10-15 19:30 +0200
      Re: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 19:40 +0200
        RE: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Gabriele Paoloni <gabriele.paoloni@huawei.com> - 2015-10-16 15:10 +0200
    Re: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Jiang Liu <jiang.liu@linux.intel.com> - 2015-10-16 07:50 +0200
      Re: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 10:50 +0200
  Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Arnd Bergmann <arnd@arndb.de> - 2015-10-15 17:50 +0200
    Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 18:10 +0200
      Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Arnd Bergmann <arnd@arndb.de> - 2015-10-15 21:20 +0200
        Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 10:10 +0200
          Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Arnd Bergmann <arnd@arndb.de> - 2015-10-16 10:50 +0200
  [PATCH RFC 5/7] genirq/msi: Add msi_domain_populate_irqs Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  [PATCH RFC 1/7] platform-msi: Allow MSIs to be allocated in chunks Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  [PATCH RFC 6/7] platform-msi: Allow creation of a MSI-based stacked irq domain Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Jiang Liu <jiang.liu@linux.intel.com> - 2015-10-16 04:00 +0200
    Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 10:50 +0200

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