Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges

From	Arnd Bergmann <arnd@arndb.de>
Newsgroups	linux.kernel
Subject	Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges
Date	2015-10-15 21:20 +0200
Message-ID	<qjWed-7ns-1@gated-at.bofh.it> (permalink)
References	<qjSNk-2aP-7@gated-at.bofh.it> <qjSX0-2mu-15@gated-at.bofh.it> <qjTgm-2Z7-15@gated-at.bofh.it>
Organization	linux.* mail to news gateway

Show all headers | View raw

On Thursday 15 October 2015 17:01:02 Marc Zyngier wrote:
> 
> "Preconfigured" is the key word. While you can do something like that if
> your hardware treats MSIs just as if they were wired interrupts
> (something like GICv2m), it becomes far more hairy if the target of MSIs
> is something like a GICv3 ITS (which is the case for HiSilicon mbigen).
> 
> The main reason is that the ITS relies on "translation tables" kept in
> memory, which the OS has to configure, and handing over pre-configured
> tables is not something I'm looking forward to doing. From a CPU point
> of view, this is akin entering the kernel with the MMU already on and no
> idmap...
> 
> The approach taken here is to make the MSI-ness explicit at the irqchip
> level, and keep the interrupting device oblivious of that feature. Also,
> this relies on the fact that we can have one MSI per wire, meaning that
> we don't have to multiplex anything (no nested irqchip), and that we can
> rely on hierarchical domains, which simplifies the code (at least for
> the irqchip).
> 

Thanks, that already makes things much clearer. Just one more question:
why can't those translation tables be configured statically by the
irqchip driver? Is this all about being able to cut a few cycles
in case of virtualization? I would assume that once you have gone through
the overhead of having both an MSI and a normal interrupt line (with
the need for serialization vs DMA), you can just as well trap to user
space to deliver an IRQ to a guest.

	Arnd
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Thread

[PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  [PATCH RFC 2/7] platform-msi: Factor out allocation/free of private data Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
    Re: [PATCH RFC 2/7] platform-msi: Factor out allocation/free of  private data Jiang Liu <jiang.liu@linux.intel.com> - 2015-10-16 07:50 +0200
      Re: [PATCH RFC 2/7] platform-msi: Factor out allocation/free of private  data Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 11:00 +0200
  [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
    RE: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Gabriele Paoloni <gabriele.paoloni@huawei.com> - 2015-10-15 19:30 +0200
      Re: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 19:40 +0200
        RE: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Gabriele Paoloni <gabriele.paoloni@huawei.com> - 2015-10-16 15:10 +0200
    Re: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Jiang Liu <jiang.liu@linux.intel.com> - 2015-10-16 07:50 +0200
      Re: [PATCH RFC 4/7] genirq/msi: Make the .prepare callback reusable Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 10:50 +0200
  Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Arnd Bergmann <arnd@arndb.de> - 2015-10-15 17:50 +0200
    Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 18:10 +0200
      Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Arnd Bergmann <arnd@arndb.de> - 2015-10-15 21:20 +0200
        Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 10:10 +0200
          Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Arnd Bergmann <arnd@arndb.de> - 2015-10-16 10:50 +0200
  [PATCH RFC 5/7] genirq/msi: Add msi_domain_populate_irqs Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  [PATCH RFC 1/7] platform-msi: Allow MSIs to be allocated in chunks Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  [PATCH RFC 6/7] platform-msi: Allow creation of a MSI-based stacked irq domain Marc Zyngier <marc.zyngier@arm.com> - 2015-10-15 17:50 +0200
  Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Jiang Liu <jiang.liu@linux.intel.com> - 2015-10-16 04:00 +0200
    Re: [PATCH RFC 0/7] Adding core support for wire-MSI bridges Marc Zyngier <marc.zyngier@arm.com> - 2015-10-16 10:50 +0200

csiph-web