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[PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield

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The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's
set the neccessary capability for that chip. See commit c54fdbb2823d (x86: Add
cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/kernel/cpu/intel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 98a13db..209ac1e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 		switch (c->x86_model) {
 		case 0x27:	/* Penwell */
 		case 0x35:	/* Cloverview */
+		case 0x4a:	/* Merrifield */
 			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
 			break;
 		default:
-- 
2.5.3

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[PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2015-10-08 18:00 +0200
  [tip:x86/cpufeature] x86/cpu/intel:   Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield tip-bot for Andy Shevchenko <tipbot@zytor.com> - 2015-10-11 21:20 +0200

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