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[PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent

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The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288
SoCs only feed those clocks, allow those clocks to change their parents
all the way up the hierarchy.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 90c1c9b..4e90252 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -317,25 +317,25 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
 	MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
 			RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
-	COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0,
+	COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
 			RK3288_CLKGATE_CON(4), 4, GFLAGS),
-	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
+	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(9), 0,
 			RK3288_CLKGATE_CON(4), 5, GFLAGS,
-		MUX(0, "spdif_mux", mux_spdif_p, 0,
+		MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
 				RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)),
-	GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 0,
+	GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
 			RK3288_CLKGATE_CON(4), 6, GFLAGS),
-	COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
+	COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
 			RK3288_CLKGATE_CON(4), 7, GFLAGS),
-	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
+	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(41), 0,
 			RK3288_CLKGATE_CON(4), 8, GFLAGS,
-		MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, 0,
+		MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
 				RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)),
-	GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 0,
+	GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
 			RK3288_CLKGATE_CON(4), 9, GFLAGS),
 
 	GATE(0, "sclk_acc_efuse", "xin24m", 0,
-- 
2.6.1

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[PATCH v4 0/8] Add SPDIF support for rockchip Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-08 15:40 +0200
  [PATCH v4 1/8] ASoC: dt-bindings: add rockchip tranceiver bindings Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-08 15:40 +0200
    Re: [PATCH v4 1/8] ASoC: dt-bindings: add rockchip tranceiver bindings Rob Herring <robh@kernel.org> - 2015-10-08 19:00 +0200
      Re: [PATCH v4 1/8] ASoC: dt-bindings: add rockchip tranceiver  bindings Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-09 14:00 +0200
  [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-08 15:40 +0200
    Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent Heiko Stuebner <heiko@sntech.de> - 2015-10-08 17:20 +0200
      Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to  change their parent Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-09 13:40 +0200
        Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent Heiko Stübner <heiko@sntech.de> - 2015-10-11 12:50 +0200
  [PATCH v4 4/8] ARM: dts: rockchip: Add SPDIF optical out on Radxa Rock Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-08 15:40 +0200
  [PATCH v4 3/8] ARM: dts: rockchip: Add SPDIF transceiver for RK3188 Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-08 15:40 +0200
  [PATCH v4 2/8] ASoC: rockchip: Add rockchip SPDIF transceiver driver Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-08 15:40 +0200
  [PATCH v4 6/8] ARM: dts: rockchip: Add SPDIF transceiver for RK3288 Sjoerd Simons <sjoerd.simons@collabora.co.uk> - 2015-10-08 15:40 +0200
  Re: [PATCH v4 0/8] Add SPDIF support for rockchip Heiko Stübner <heiko@sntech.de> - 2015-10-14 00:00 +0200

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