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Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management module driver

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2015-09-29 16:55 GMT+08:00 Lee Jones <lee.jones@linaro.org>:
> On Tue, 29 Sep 2015, Barry Song wrote:
>
>> 2015-09-29 15:16 GMT+08:00 Lee Jones <lee.jones@linaro.org>:
>> > On Tue, 29 Sep 2015, Barry Song wrote:
>> >> >> >> +static int sirfsoc_pwrc_probe(struct platform_device *pdev)
>> >> >> >> +{
>> >> >> >> +     struct device_node *np = pdev->dev.of_node;
>> >> >> >> +     const struct of_device_id *match;
>> >> >> >> +     struct sirfsoc_pwrc_info *pwrcinfo;
>> >> >> >> +     struct regmap_irq_chip *regmap_irq_chip;
>> >> >> >> +     struct sirfsoc_pwrc_register *pwrc_reg;
>> >> >> >> +     struct regmap *map;
>> >> >> >> +     int ret;
>> >> >> >> +     u32 base;
>> >> >> >> +
>> >> >> >> +     if (of_property_read_u32(np, "reg", &base))
>> >> >> >> +             panic("unable to find base address of pwrc node in dtb\n");
>> >> >> >
>> >> >> > It looks like this driver should depend on OF.
>> >> >> >
>> >> >> > Why are you obtaining the base address manually? Use:
>> >> >> >
>> >> >> >   res = platform_get_resource();
>> >> >> >   devm_ioremap_resource(res);
>> >> >> >
>> >> >> > ... instead.
>> >> >>
>> >> >> this was explained as they are not in memory space, they are behind a
>> >> >> bus bridge.
>> >> >
>> >> > Use 'ranges' in the DT, then you can pull out the proper address
>> >> > without hand rolling your own method.
>> >>
>> >> it seems it is not a "ranges" thing,  things behind rtciobrg is much
>> >> like things behind USB or sdio. we need to use a rtciobrg protocol to
>> >> do read/write.
>> >> they can not be randomly accessed by load/store, and can't be XIP.
>> >> they don't have any ranges in CPU memory space.
>> >
>> > So what's the point of 'base' then?  I assumed this was the base of
>> > the IP registers which where memory mapped?
>>
>> just think we have a i2c device, and this i2c device has multi-functions.
>> each function has a base of its register offset.
>> actually, the base is the offset of 1st register.
>
> Does it every change, from device to device?

yes. Lee. e.g:

                        rtc-iobg@18840000 {
                                reg = <0x18840000 0x1000>;

                                sysrtc@2000 {
                                        compatible = "sirf,prima2-sysrtc";
                                        reg = <0x2000 0x100>;
                                        interrupts = <0 52 0>;
                                };
                                pwrc@3000 {
                                        compatible = "sirf,atlas7-pwrc";
                                        reg = <0x3000 0x100>;
                                        interrupts = <0 32 0>;
                                };

                        }


-barry
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Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Lee Jones <lee.jones@linaro.org> - 2015-09-24 20:20 +0200
  Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Barry Song <21cnbao@gmail.com> - 2015-09-29 08:20 +0200
    Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Lee Jones <lee.jones@linaro.org> - 2015-09-29 09:20 +0200
      Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Barry Song <21cnbao@gmail.com> - 2015-09-29 10:40 +0200
        Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Lee Jones <lee.jones@linaro.org> - 2015-09-29 11:00 +0200
          Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Barry Song <21cnbao@gmail.com> - 2015-10-04 12:10 +0200
            Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Lee Jones <lee.jones@linaro.org> - 2015-10-05 10:30 +0200
              Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Barry Song <21cnbao@gmail.com> - 2015-10-05 12:10 +0200
                Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management  module driver Lee Jones <lee.jones@linaro.org> - 2015-10-05 12:30 +0200

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