Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]


Groups > linux.kernel > #1236212

Re: [V4 PATCH 2/4] panic/x86: Allow cpus to save registers even if they are looping in NMI context

From Peter Zijlstra <peterz@infradead.org>
Newsgroups linux.kernel
Subject Re: [V4 PATCH 2/4] panic/x86: Allow cpus to save registers even if they are looping in NMI context
Date 2015-09-30 14:00 +0200
Message-ID <qeodc-468-13@gated-at.bofh.it> (permalink)
References <qczZ7-T1-7@gated-at.bofh.it> <qczZ9-T1-31@gated-at.bofh.it>
Organization linux.* mail to news gateway

Show all headers | View raw


On Fri, Sep 25, 2015 at 08:28:07PM +0900, Hidehiro Kawai wrote:
> --- a/arch/x86/kernel/reboot.c
> +++ b/arch/x86/kernel/reboot.c
> @@ -718,6 +718,7 @@ void machine_crash_shutdown(struct pt_regs *regs)
>  static nmi_shootdown_cb shootdown_callback;
>  
>  static atomic_t waiting_for_crash_ipi;
> +static int crash_ipi_done;
>  
>  static int crash_nmi_callback(unsigned int val, struct pt_regs *regs)
>  {
> @@ -779,6 +780,7 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback)
>  	wmb();
>  
>  	smp_send_nmi_allbutself();
> +	crash_ipi_done = 1; /* Kick cpus looping in nmi context */

I would suggest using WRITE_ONCE() for that, because without the
volatile the compiler need not actually emit the store until after the
whole waiting thing _IF_ it can inline the whole thing.

Currently udelay() will end up being a function call and will therefore
force the store to be emitted, but I'd rather not rely on that.

>  
>  	msecs = 1000; /* Wait at most a second for the other cpus to stop */
>  	while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) {
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Back to linux.kernel | Previous | NextPrevious in thread | Next in thread | Find similar | Unroll thread


Thread

[V4 PATCH 0/4] Fix race issues among panic, NMI and crash_kexec Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com> - 2015-09-25 14:10 +0200
  [V4 PATCH 3/4] kexec: Fix race between panic() and crash_kexec()  called directly Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com> - 2015-09-25 14:10 +0200
    Re: [V4 PATCH 3/4] kexec: Fix race between panic() and crash_kexec()  called directly kbuild test robot <lkp@intel.com> - 2015-09-28 06:10 +0200
      RE: Re: [V4 PATCH 3/4] kexec: Fix race between panic() and  crash_kexec() called directly 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-09-28 06:50 +0200
    RE: Re: [V4 PATCH 3/4] kexec: Fix race between panic() and  crash_kexec() called directly 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-09-28 09:10 +0200
      Re: Re: [V4 PATCH 3/4] kexec: Fix race between panic() and  crash_kexec() called directly Peter Zijlstra <peterz@infradead.org> - 2015-09-30 14:00 +0200
        RE: Re: [V4 PATCH 3/4] kexec: Fix race between panic() and  crash_kexec() called directly 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-01 04:10 +0200
  [V4 PATCH 1/4] panic/x86: Fix re-entrance problem due to panic on  NMI Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com> - 2015-09-25 14:10 +0200
    RE: [V4 PATCH 1/4] panic/x86: Fix re-entrance problem due to panic  on NMI 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-09-25 14:20 +0200
      Re: [V4 PATCH 1/4] panic/x86: Fix re-entrance problem due to panic  on NMI Peter Zijlstra <peterz@infradead.org> - 2015-09-30 13:30 +0200
        RE: [V4 PATCH 1/4] panic/x86: Fix re-entrance problem due to panic  on NMI 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-01 03:10 +0200
  [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com> - 2015-09-25 14:10 +0200
    Re: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Peter Zijlstra <peterz@infradead.org> - 2015-09-30 14:00 +0200
      RE: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-01 04:40 +0200
        Re: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Peter Zijlstra <peterz@infradead.org> - 2015-10-01 08:30 +0200
          RE: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-01 09:10 +0200
            Re: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Borislav Petkov <bp@alien8.de> - 2015-10-01 10:50 +0200
              RE: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-01 12:30 +0200
                Re: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Borislav Petkov <bp@alien8.de> - 2015-10-01 13:10 +0200
                RE: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-02 03:00 +0200
                Re: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Borislav Petkov <bp@alien8.de> - 2015-10-02 09:50 +0200
                RE: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-05 04:10 +0200
                Re: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Borislav Petkov <bp@alien8.de> - 2015-10-05 10:30 +0200
                RE: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-05 11:30 +0200
                Re: [V4 PATCH 4/4] x86/apic: Introduce noextnmi boot option Borislav Petkov <bp@alien8.de> - 2015-10-05 12:20 +0200
  [V4 PATCH 2/4] panic/x86: Allow cpus to save registers even if they  are looping in NMI context Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com> - 2015-09-25 14:10 +0200
    Re: [V4 PATCH 2/4] panic/x86: Allow cpus to save registers even if  they are looping in NMI context Peter Zijlstra <peterz@infradead.org> - 2015-09-30 14:00 +0200
      RE: [V4 PATCH 2/4] panic/x86: Allow cpus to save registers even if  they are looping in NMI context 河合英宏 / KAWAI,HIDEHIRO   <hidehiro.kawai.ez@hitachi.com> - 2015-10-01 03:50 +0200

csiph-web