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Re: [PATCH v5 4/6] irqchip, gicv3-its: Add HW revision detection and configuration

From Marc Zyngier <marc.zyngier@arm.com>
Newsgroups linux.kernel
Subject Re: [PATCH v5 4/6] irqchip, gicv3-its: Add HW revision detection and configuration
Date 2015-09-22 19:00 +0200
Message-ID <qbz58-2KT-25@gated-at.bofh.it> (permalink)
References <qbglQ-Z6-17@gated-at.bofh.it> <qbgvv-1pI-1@gated-at.bofh.it>
Organization ARM Ltd

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On Mon, 21 Sep 2015 22:58:37 +0200
Robert Richter <rric@kernel.org> wrote:

> From: Robert Richter <rrichter@cavium.com>
> 
> Some GIC revisions require an individual configuration to esp. add
> workarounds for HW bugs. This patch implements generic code to parse
> the hw revision provided by an IIDR register value and runs specific
> code if hw matches. A function is added that reads the IIDR registers
> for ITS (GITS_IIDR) and then goes through a list of init functions to
> be called for specific versions. Same could be done for GICV3
> (GICD_IIDR), but there are no users yet for it.
> 
> The patch is needed to implement workarounds for HW errata in Cavium's
> ThunderX GICV3 ITS.
> 
> v5:
>  * renamed caps names to quirk
> 
> v4:
>  * only enable hw detection for its in its_enable_quirks()
>  * removed gicv3_check_capabilities()
> 
> v3:
>  * use arm64 errata framework for midr check
> 
> v2:
>  * adding MIDR check
> 
> Signed-off-by: Robert Richter <rrichter@cavium.com>

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>

	M.
-- 
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Thread

[PATCH v5 0/6] irqchip, gicv3: Updates and Cavium ThunderX errata workarounds Robert Richter <rric@kernel.org> - 2015-09-21 23:00 +0200
  [PATCH v5 4/6] irqchip, gicv3-its: Add HW revision detection and configuration Robert Richter <rric@kernel.org> - 2015-09-21 23:10 +0200
    Re: [PATCH v5 4/6] irqchip, gicv3-its: Add HW revision detection  and configuration Marc Zyngier <marc.zyngier@arm.com> - 2015-09-22 19:00 +0200
    [tip:irq/core] irqchip/gicv3-its:   Add HW revision detection and configuration tip-bot for Robert Richter <tipbot@zytor.com> - 2015-09-29 10:20 +0200
  [PATCH v5 1/6] irqchip, gicv3-its: Add range check for number of allocated pages Robert Richter <rric@kernel.org> - 2015-09-21 23:10 +0200
    [tip:irq/core] irqchip/gicv3-its:   Add range check for number of allocated pages tip-bot for Robert Richter <tipbot@zytor.com> - 2015-09-29 10:20 +0200
  [PATCH v5 2/6] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154 Robert Richter <rric@kernel.org> - 2015-09-21 23:10 +0200
    Re: [PATCH v5 2/6] irqchip, gicv3: Workaround for Cavium ThunderX  erratum 23154 Marc Zyngier <marc.zyngier@arm.com> - 2015-09-22 19:00 +0200
    [tip:irq/core] irqchip/gicv3:   Workaround for Cavium ThunderX erratum 23154 tip-bot for Robert Richter <tipbot@zytor.com> - 2015-09-29 10:20 +0200
  Re: [PATCH v5 0/6] irqchip, gicv3: Updates and Cavium ThunderX  errata workarounds Marc Zyngier <marc.zyngier@arm.com> - 2015-09-22 19:00 +0200
    Re: [PATCH v5 0/6] irqchip, gicv3: Updates and Cavium ThunderX  errata workarounds Marc Zyngier <marc.zyngier@arm.com> - 2015-09-22 20:10 +0200
      Re: [PATCH v5 0/6] irqchip, gicv3: Updates and Cavium ThunderX  errata workarounds Will Deacon <will.deacon@arm.com> - 2015-09-22 20:30 +0200
        Re: [PATCH v5 0/6] irqchip, gicv3: Updates and Cavium ThunderX  errata workarounds Marc Zyngier <marc.zyngier@arm.com> - 2015-09-22 21:50 +0200
          Re: [PATCH v5 0/6] irqchip, gicv3: Updates and Cavium ThunderX  errata workarounds Catalin Marinas <catalin.marinas@arm.com> - 2015-09-24 19:00 +0200

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