Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1326223
| From | Krzysztof Adamski <k@japko.eu> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v3 2/5] dts: sun8i-h3: Add APB0 related clocks and resets |
| Date | 2016-02-04 00:40 +0100 |
| Message-ID | <qYfbJ-uu-43@gated-at.bofh.it> (permalink) |
| References | <qYfbI-uu-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.
After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..bb37f52 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -276,6 +276,24 @@
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
+
+ apb0: apb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01f01428 {
+ compatible = "allwinner,sun8i-h3-apb0-gates-clk";
+ reg = <0x01f01428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <1>;
+ clock-output-names = "apb0_pio", "apb0_ir";
+ };
};
soc {
@@ -493,5 +511,11 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ apb0_reset: reset@01f014b0 {
+ reg = <0x01f014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
};
};
--
2.1.4
Back to linux.kernel | Previous | Next — Previous in thread | Find similar | Unroll thread
[PATCH v3 0/5] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
[PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
Re: [PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support Chen-Yu Tsai <wens@csie.org> - 2016-02-05 10:50 +0100
Re: [PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 10:50 +0100
[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Jean-Francois Moine <moinejf@free.fr> - 2016-02-04 15:50 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-04 22:00 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 12:20 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 12:20 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-05 13:00 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Jean-Francois Moine <moinejf@free.fr> - 2016-02-06 11:30 +0100
[PATCH v3 2/5] dts: sun8i-h3: Add APB0 related clocks and resets Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
csiph-web