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Groups > linux.kernel > #1327607
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 |
| Date | 2016-02-05 12:20 +0100 |
| Message-ID | <qYMAG-7S6-13@gated-at.bofh.it> (permalink) |
| References | <qYfbI-uu-5@gated-at.bofh.it> <qYfbJ-uu-47@gated-at.bofh.it> <qYtom-3f9-19@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
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Hi, On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote: > On Thu, 4 Feb 2016 00:33:46 +0100 > Krzysztof Adamski <k@japko.eu> wrote: > > > This patch adds support for APB0 in H3. It seems to be compatible with > > earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR, > > etc). > > > > Signed-off-by: Krzysztof Adamski <k@japko.eu> > > --- > > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > > drivers/clk/sunxi/clk-simple-gates.c | 2 ++ > > 2 files changed, 3 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > > index e59f57b..751c8b9f0 100644 > > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > > @@ -45,6 +45,7 @@ Required properties: > > "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 > > "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 > > "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 > > + "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3 > > "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 > > "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock > > "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 > > diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c > > index f4da52b..6753c87 100644 > > --- a/drivers/clk/sunxi/clk-simple-gates.c > > +++ b/drivers/clk/sunxi/clk-simple-gates.c > > @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk", > > sunxi_simple_gates_init); > > CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk", > > sunxi_simple_gates_init); > > +CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk", > > + sunxi_simple_gates_init); > > CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk", > > sunxi_simple_gates_init); > > CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk", > > It seems that the other compatible strings are there for historical > reasons. Why do you need a new one with such a specific name? > > It would have been more sensible to add a generic compatible string as > "allwinner,apb-gates", letting the removal of the other strings for a > later patch... Yeah, it's a good idea, and it's probably time that we move to that. However, I'd like to keep per-soc and per-clocks compatibles in the DT, in case we need to protect a clock in the future. That doesn't prevent to have two compatibles thoughe, the specific and the generic. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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[PATCH v3 0/5] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
[PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
Re: [PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support Chen-Yu Tsai <wens@csie.org> - 2016-02-05 10:50 +0100
Re: [PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 10:50 +0100
[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Jean-Francois Moine <moinejf@free.fr> - 2016-02-04 15:50 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-04 22:00 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 12:20 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 12:20 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-05 13:00 +0100
Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Jean-Francois Moine <moinejf@free.fr> - 2016-02-06 11:30 +0100
[PATCH v3 2/5] dts: sun8i-h3: Add APB0 related clocks and resets Krzysztof Adamski <k@japko.eu> - 2016-02-04 00:40 +0100
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