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[PATCH V2 5/6] coresight-stm: Bindings for System Trace Macrocell

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From: Mathieu Poirier <mathieu.poirier@linaro.org>

The System Trace Macrocell (STM) is an IP block falling under the
CoreSight umbrella.  It's main purpose it so expose stimulus channels
to any system component for the purpose of information logging.

Bindings for this IP block adds a couple of items to the current
mandatory definition for CoreSight components.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
---
 .../devicetree/bindings/arm/coresight.txt          | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 62938eb..93147c0c 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -19,6 +19,7 @@ its hardware characteristcs.
 		- "arm,coresight-etm3x", "arm,primecell";
 		- "arm,coresight-etm4x", "arm,primecell";
 		- "qcom,coresight-replicator1x", "arm,primecell";
+		- "arm,coresight-stm", "arm,primecell"; [1]
 
 	* reg: physical base address and length of the register
 	  set(s) of the component.
@@ -36,6 +37,14 @@ its hardware characteristcs.
 	  layout using the generic DT graph presentation found in
 	  "bindings/graph.txt".
 
+* Additional required properties for System Trace Macrocells (STM):
+	* reg: along with the physical base address and length of the register
+	  set as described above, another entry is required to describe the
+	  mapping of the extended stimulus port area.
+
+	* reg-names: the only acceptable values are "stm-base" and
+	  "stm-stimulus-base", each corresponding to the areas defined in "reg".
+
 * Required properties for devices that don't show up on the AMBA bus, such as
   non-configurable replicators:
 
@@ -202,3 +211,22 @@ Example:
 			};
 		};
 	};
+
+4. STM
+	stm@20100000 {
+		compatible = "arm,coresight-stm", "arm,primecell";
+		reg = <0 0x20100000 0 0x1000>,
+		      <0 0x28000000 0 0x180000>;
+		reg-names = "stm-base", "stm-stimulus-base";
+
+		clocks = <&soc_smc50mhz>;
+		clock-names = "apb_pclk";
+		port {
+			stm_out_port: endpoint {
+				remote-endpoint = <&main_funnel_in_port2>;
+			};
+		};
+	};
+
+[1]. There is currently two version of STM: STM32 and STM500.  Both
+have the same HW interface and as such don't need an explicit binding name.
-- 
1.9.1

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Thread

[PATCH V2 0/6] Introduce CoreSight STM support Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
  [PATCH V2 5/6] coresight-stm: Bindings for System Trace Macrocell Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
  [PATCH V2 4/6] Documentations: Add explanations of the case for non-configurable masters Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
  [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
    Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-05 14:00 +0100
      RE: [PATCH V2 3/6] stm class: provision for statically assigned  masterIDs Mike Leach <Mike.Leach@arm.com> - 2016-02-05 17:40 +0100
        RE: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-08 12:00 +0100
      Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-05 19:10 +0100
        Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-08 14:30 +0100
          Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-08 18:10 +0100
            RE: [PATCH V2 3/6] stm class: provision for statically assigned  masterIDs Al Grant <Al.Grant@arm.com> - 2016-02-08 18:50 +0100
  [PATCH V2 1/6] stm class: Add ioctl get_options interface Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
    Re: [PATCH V2 1/6] stm class: Add ioctl get_options interface Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-05 14:00 +0100
  [PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
    Re: [PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-05 14:10 +0100
      Re: [PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component Arnd Bergmann <arnd@arndb.de> - 2016-02-05 15:40 +0100

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