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Groups > linux.kernel > #1327806
| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component |
| Date | 2016-02-05 15:40 +0100 |
| Message-ID | <qYPIf-1t6-33@gated-at.bofh.it> (permalink) |
| References | <qY0Po-7NH-7@gated-at.bofh.it> <qY0Pp-7NH-27@gated-at.bofh.it> <qYOja-ED-57@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Friday 05 February 2016 15:06:20 Alexander Shishkin wrote:
> Chunyan Zhang <zhang.chunyan@linaro.org> writes:
>
> > +#ifndef CONFIG_64BIT
> > +static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
> > +{
> > + asm volatile("strd %1, %0"
> > + : "+Qo" (*(volatile u64 __force *)addr)
> > + : "r" (val));
> > +}
>
> Is it really ok to do this for all !64bit arms, inside a driver, just
> like that? I'm not an expert, but I'm pretty sure there's more to it.
It's normally device dependent whether this works or not, on 32-bit
architectures, a 64-bit access to an I/O bus tends to get split into
two 32 bit accesses and the order might not be the as what was
intended.
We have functions in include/linux/io-64-nonatomic-hi-lo.h
and include/linux/io-64-nonatomic-lo-hi.h that are meant to
do this right. Maybe the driver can be changed to use whichever
one is correct for it.
Arnd
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[PATCH V2 0/6] Introduce CoreSight STM support Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
[PATCH V2 5/6] coresight-stm: Bindings for System Trace Macrocell Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
[PATCH V2 4/6] Documentations: Add explanations of the case for non-configurable masters Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
[PATCH V2 3/6] stm class: provision for statically assigned masterIDs Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-05 14:00 +0100
RE: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Mike Leach <Mike.Leach@arm.com> - 2016-02-05 17:40 +0100
RE: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-08 12:00 +0100
Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-05 19:10 +0100
Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-08 14:30 +0100
Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-08 18:10 +0100
RE: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs Al Grant <Al.Grant@arm.com> - 2016-02-08 18:50 +0100
[PATCH V2 1/6] stm class: Add ioctl get_options interface Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
Re: [PATCH V2 1/6] stm class: Add ioctl get_options interface Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-05 14:00 +0100
[PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component Chunyan Zhang <zhang.chunyan@linaro.org> - 2016-02-03 09:20 +0100
Re: [PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-02-05 14:10 +0100
Re: [PATCH V2 6/6] coresight-stm: adding driver for CoreSight STM component Arnd Bergmann <arnd@arndb.de> - 2016-02-05 15:40 +0100
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