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Groups > linux.kernel > #1320717
| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 11/13] dtb: amd: Add PCIe SMMU device tree node |
| Date | 2016-01-28 15:20 +0100 |
| Message-ID | <qVVAu-4Ce-9@gated-at.bofh.it> (permalink) |
| References | <qVFFn-1hk-3@gated-at.bofh.it> <qVSMh-2B1-5@gated-at.bofh.it> <qVTS2-3iP-11@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Thursday 28 January 2016 12:20:58 Robin Murphy wrote: > > > > Will, Robin, thoughts? > > Any IDs specified here would only apply to DMA by the "platform device" > side of the host controller itself (as would an equivalent "iommus" > property on pcie0 once I finish the SMMUv2 generic binding support I'm > working on). In terms of PCI devices, the "mmu-masters" property is > overloaded such that only its existence matters, to identify that there > _is_ a relationship between the SMMU and the PCI bus(es) behind that > host controller. I wasn't aware that this was actually still specified. I had hoped we were getting rid of mmu-masters before anyone actually started using it, but now I see it in ns2.dtsi and fsl-ls2080a.dtsi. Does anyone know what happened to the plan to use the iommu DT binding for the ARM SMMU instead? Do we now have to support both ways indefinitely? Arnd
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Re: [PATCH 11/13] dtb: amd: Add PCIe SMMU device tree node Mark Rutland <mark.rutland@arm.com> - 2016-01-28 12:20 +0100
Re: [PATCH 11/13] dtb: amd: Add PCIe SMMU device tree node Robin Murphy <robin.murphy@arm.com> - 2016-01-28 13:30 +0100
Re: [PATCH 11/13] dtb: amd: Add PCIe SMMU device tree node Arnd Bergmann <arnd@arndb.de> - 2016-01-28 15:20 +0100
Re: [PATCH 11/13] dtb: amd: Add PCIe SMMU device tree node Will Deacon <will.deacon@arm.com> - 2016-01-28 15:30 +0100
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