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[PATCH v2 06/26] clk: sunxi: Add PLL3 clock

From Maxime Ripard <maxime.ripard@free-electrons.com>
Newsgroups linux.kernel
Subject [PATCH v2 06/26] clk: sunxi: Add PLL3 clock
Date 2016-01-14 16:30 +0100
Message-ID <qQS0z-uX-45@gated-at.bofh.it> (permalink)
References <qQS0x-uX-7@gated-at.bofh.it>
Organization linux.* mail to news gateway

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The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile                        |  1 +
 drivers/clk/sunxi/clk-sun4i-pll3.c                | 90 +++++++++++++++++++++++
 3 files changed, 92 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 5360554a7d3f..bb9fb78dcff8 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,6 +10,7 @@ Required properties:
 	"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
 	"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
 	"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+	"allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
 	"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
 	"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
 	"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index a991cd8ca509..40c32ffd912c 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun4i-display.o
+obj-y += clk-sun4i-pll3.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun4i-pll3.c b/drivers/clk/sunxi/clk-sun4i-pll3.c
new file mode 100644
index 000000000000..6c9c2210b6b2
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-pll3.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define SUN4I_A10_PLL3_GATE_BIT	31
+#define SUN4I_A10_PLL3_DIV_WIDTH	7
+#define SUN4I_A10_PLL3_DIV_SHIFT	0
+
+static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
+
+static void __init sun4i_a10_pll3_setup(struct device_node *node)
+{
+	const char *clk_name = node->name, *parent;
+	struct clk_multiplier *mult;
+	struct clk_gate *gate;
+	void __iomem *reg;
+	struct clk *clk;
+	int ret;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	parent = of_clk_get_parent_name(node, 0);
+
+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+	if (IS_ERR(reg)) {
+		pr_err("%s: Could not map the clock registers\n", clk_name);
+		return;
+	}
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return;
+
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
+	gate->lock = &sun4i_a10_pll3_lock;
+
+	mult = kzalloc(sizeof(*mult), GFP_KERNEL);
+	if (!mult)
+		goto err_free_gate;
+
+	mult->reg = reg;
+	mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
+	mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
+	mult->lock = &sun4i_a10_pll3_lock;
+
+	clk = clk_register_composite(NULL, clk_name,
+				     &parent, 1,
+				     NULL, NULL,
+				     &mult->hw, &clk_multiplier_ops,
+				     &gate->hw, &clk_gate_ops,
+				     0);
+	if (IS_ERR(clk)) {
+		pr_err("%s: Couldn't register the clock\n", clk_name);
+		goto err_free_mult;
+	}
+
+	ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(ret))
+		goto err_clk_unregister;
+
+	return;
+
+err_clk_unregister:
+	clk_unregister_composite(clk);
+err_free_mult:
+	kfree(mult);
+err_free_gate:
+	kfree(gate);
+}
+
+CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
+	       sun4i_a10_pll3_setup);
-- 
2.6.4

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Thread

[PATCH v2 00/26] drm: Add Allwinner A10 display engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 03/26] clk: Add regmap support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 22/26] ARM: sun5i: r8: Add display blocks to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 20/26] drm: sun4i: tv: Add PAL output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 21/26] drm: sun4i: tv: Add NTSC output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 10/26] ARM: sun5i: a13: Add display and TCON clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 18/26] drm: sun4i: Add RGB output Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 23/26] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 11/26] ARM: sun5i: Add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 19/26] drm: sun4i: Add composite output Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 08/26] clk: sun5i: add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
    Re: [PATCH v2 08/26] clk: sun5i: add DRAM gates Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
  [PATCH v2 06/26] clk: sunxi: Add PLL3 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
    Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
  [PATCH v2 04/26] clk: composite: Add unregister function Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
  [PATCH v2 02/26] reset: Make reset_control_ops const Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
  [PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
    Re: [PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
  [PATCH v2 26/26] DO NOT MERGE: ARM: sun5i: chip: Enable the LCD panel Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
  [PATCH v2 15/26] drm/modes: Support modes names on the command line Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
  [PATCH v2 14/26] drm/modes: Rewrite the command line parser Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
  [PATCH v2 17/26] drm: sun4i: Add DT bindings documentation Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
    Re: [PATCH v2 17/26] drm: sun4i: Add DT bindings documentation Rob Herring <robh@kernel.org> - 2016-01-15 04:20 +0100
  [PATCH v2 12/26] ARM: sun5i: Add TV encoder gate to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
  [PATCH v2 25/26] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
    Re: [PATCH v2 25/26] drm/panel: simple: Add timings for the Olimex  LCD-OLinuXino-4.3TS Rob Herring <robh@kernel.org> - 2016-01-15 04:20 +0100
  [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
    Re: [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2016-01-15 00:20 +0100
  [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
    Re: [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
  [PATCH v2 24/26] devicetree: Add olimex vendor prefix Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
    Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix Rob Herring <robh@kernel.org> - 2016-01-15 04:20 +0100
      Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix Stefan Wahren <stefan.wahren@i2se.com> - 2016-01-15 07:50 +0100
        Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-15 09:10 +0100
  [PATCH v2 09/26] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
  [PATCH v2 01/26] reset: Move DT cell size check to the core Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:50 +0100

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