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[tip:x86/asm] x86/fpu: Disable AVX when eagerfpu is off

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Commit-ID:  394db20ca240741a08d472173db13d6f6a6e5a28
Gitweb:     http://git.kernel.org/tip/394db20ca240741a08d472173db13d6f6a6e5a28
Author:     yu-cheng yu <yu-cheng.yu@intel.com>
AuthorDate: Wed, 6 Jan 2016 14:24:54 -0800
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 12 Jan 2016 11:51:21 +0100

x86/fpu: Disable AVX when eagerfpu is off

When "eagerfpu=off" is given as a command-line input, the kernel
should disable AVX support.

The Task Switched bit used for lazy context switching does not
support AVX. If AVX is enabled without eagerfpu context
switching, one task's AVX state could become corrupted or leak
to other tasks. This is a bug and has bad security implications.

This only affects systems that have AVX/AVX2/AVX512 and this
issue will be found only when one actually uses AVX/AVX2/AVX512
_AND_ does eagerfpu=off.

Reference: Intel Software Developer's Manual Vol. 3A

Sec. 2.5 Control Registers:
TS Task Switched bit (bit 3 of CR0) -- Allows the saving of the
x87 FPU/ MMX/SSE/SSE2/SSE3/SSSE3/SSE4 context on a task switch
to be delayed until an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4
instruction is actually executed by the new task.

Sec. 13.4.1 Using the TS Flag to Control the Saving of the X87
FPU and SSE State
When the TS flag is set, the processor monitors the instruction
stream for x87 FPU, MMX, SSE instructions. When the processor
detects one of these instructions, it raises a
device-not-available exeception (#NM) prior to executing the
instruction.

Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bp@suse.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Quentin Casasnovas <quentin.casasnovas@oracle.com>
Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
Cc: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: yu-cheng yu <yu-cheng.yu@intel.com>
Link: http://lkml.kernel.org/r/1452119094-7252-5-git-send-email-yu-cheng.yu@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/include/asm/fpu/xstate.h | 11 ++++++-----
 arch/x86/kernel/fpu/init.c        |  6 ++++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h
index 3a6c89b..af30fde 100644
--- a/arch/x86/include/asm/fpu/xstate.h
+++ b/arch/x86/include/asm/fpu/xstate.h
@@ -20,15 +20,16 @@
 
 /* Supported features which support lazy state saving */
 #define XFEATURE_MASK_LAZY	(XFEATURE_MASK_FP | \
-				 XFEATURE_MASK_SSE | \
+				 XFEATURE_MASK_SSE)
+
+/* Supported features which require eager state saving */
+#define XFEATURE_MASK_EAGER	(XFEATURE_MASK_BNDREGS | \
+				 XFEATURE_MASK_BNDCSR | \
 				 XFEATURE_MASK_YMM | \
-				 XFEATURE_MASK_OPMASK |	\
+				 XFEATURE_MASK_OPMASK | \
 				 XFEATURE_MASK_ZMM_Hi256 | \
 				 XFEATURE_MASK_Hi16_ZMM)
 
-/* Supported features which require eager state saving */
-#define XFEATURE_MASK_EAGER	(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)
-
 /* All currently supported features */
 #define XCNTXT_MASK	(XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER)
 
diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c
index f0ab368..6d9f0a7 100644
--- a/arch/x86/kernel/fpu/init.c
+++ b/arch/x86/kernel/fpu/init.c
@@ -300,6 +300,12 @@ u64 __init fpu__get_supported_xfeatures_mask(void)
 static void __init fpu__clear_eager_fpu_features(void)
 {
 	setup_clear_cpu_cap(X86_FEATURE_MPX);
+	setup_clear_cpu_cap(X86_FEATURE_AVX);
+	setup_clear_cpu_cap(X86_FEATURE_AVX2);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512F);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512PF);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512ER);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512CD);
 }
 
 /*

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[PATCH 0/4] x86/fpu: FPU init code bugfixes yu-cheng yu <yu-cheng.yu@intel.com> - 2016-01-06 23:40 +0100
  [PATCH 2/4] x86/fpu: Disable XGETBV1 when no XSAVE yu-cheng yu <yu-cheng.yu@intel.com> - 2016-01-06 23:40 +0100
    [tip:x86/asm] x86/fpu: Disable XGETBV1 when no XSAVE tip-bot for yu-cheng yu <tipbot@zytor.com> - 2016-01-12 13:10 +0100
  [PATCH 3/4] x86/fpu: Disable MPX when eagerfpu is off yu-cheng yu <yu-cheng.yu@intel.com> - 2016-01-06 23:40 +0100
    [tip:x86/asm] x86/fpu: Disable MPX when eagerfpu is off tip-bot for yu-cheng yu <tipbot@zytor.com> - 2016-01-12 13:10 +0100
  [PATCH 4/4] x86/fpu: Disable AVX when eagerfpu is off yu-cheng yu <yu-cheng.yu@intel.com> - 2016-01-06 23:40 +0100
    [tip:x86/asm] x86/fpu: Disable AVX when eagerfpu is off tip-bot for yu-cheng yu <tipbot@zytor.com> - 2016-01-12 13:10 +0100
  [PATCH 1/4] x86/fpu: Fix early fpu command-line parsing yu-cheng yu <yu-cheng.yu@intel.com> - 2016-01-06 23:40 +0100
    [tip:x86/asm] x86/fpu: Fix early FPU command-line parsing tip-bot for yu-cheng yu <tipbot@zytor.com> - 2016-01-12 13:10 +0100

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