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[PATCH v5 4/5] ARM: dts: apq8064: add pcie devicetree node

From Stanimir Varbanov <stanimir.varbanov@linaro.org>
Newsgroups linux.kernel
Subject [PATCH v5 4/5] ARM: dts: apq8064: add pcie devicetree node
Date 2015-12-18 13:50 +0100
Message-ID <qH2DW-5IP-49@gated-at.bofh.it> (permalink)
References <qH2ud-5E7-11@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Add the pcie dt node so that it can probe and used.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi |   36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 1a57278cb818..495807eab8f3 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -705,5 +705,41 @@
 			compatible = "qcom,tcsr-apq8064", "syscon";
 			reg = <0x1a400000 0x100>;
 		};
+
+		pcie: pci@1b500000 {
+			compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
+			reg = <0x1b500000 0x1000
+			       0x1b502000 0x80
+			       0x1b600000 0x100
+			       0x0ff00000 0x100000>;
+			reg-names = "dbi", "elbi", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
+				  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
+			interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+			clocks = <&gcc PCIE_A_CLK>,
+				 <&gcc PCIE_H_CLK>,
+				 <&gcc PCIE_PHY_REF_CLK>;
+			clock-names = "core", "iface", "phy";
+			resets = <&gcc PCIE_ACLK_RESET>,
+				 <&gcc PCIE_HCLK_RESET>,
+				 <&gcc PCIE_POR_RESET>,
+				 <&gcc PCIE_PCI_RESET>,
+				 <&gcc PCIE_PHY_RESET>;
+			reset-names = "axi", "ahb", "por", "pci", "phy";
+			status = "disabled";
+		};
 	};
 };
-- 
1.7.9.5

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Thread

[PATCH v5 0/5] Qualcomm PCIe driver and designware fixes Stanimir Varbanov <stanimir.varbanov@linaro.org> - 2015-12-18 13:40 +0100
  [PATCH v5 5/5] ARM: dts: ifc6410: enable pcie dt node for this board Stanimir Varbanov <stanimir.varbanov@linaro.org> - 2015-12-18 13:40 +0100
  [PATCH v5 4/5] ARM: dts: apq8064: add pcie devicetree node Stanimir Varbanov <stanimir.varbanov@linaro.org> - 2015-12-18 13:50 +0100
  [PATCH v5 3/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov <stanimir.varbanov@linaro.org> - 2015-12-18 14:00 +0100
    [PATCH] PCI: qcom: fix ptr_ret.cocci warnings kbuild test robot <lkp@intel.com> - 2015-12-18 14:50 +0100
    Re: [PATCH v5 3/5] PCI: qcom: Add Qualcomm PCIe controller driver kbuild test robot <lkp@intel.com> - 2015-12-18 14:50 +0100
      Re: [PATCH v5 3/5] PCI: qcom: Add Qualcomm PCIe controller driver Bjorn Andersson <bjorn@kryo.se> - 2015-12-21 00:20 +0100
        Re: [PATCH v5 3/5] PCI: qcom: Add Qualcomm PCIe controller driver Arnd Bergmann <arnd@arndb.de> - 2015-12-22 00:10 +0100

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