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Groups > linux.kernel > #1159982
| From | David Decotigny <ddecotig@gmail.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion |
| Date | 2015-06-07 02:40 +0200 |
| Message-ID | <pywN4-8f6-5@gated-at.bofh.it> (permalink) |
| References | <pywN4-8f6-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Source and destination have the same little-endian annotation: this patch removes forced conversion from host byte order to little-endian. This addresses the following sparse warning: drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56: warning: incorrect type in argument 1 (different base types) drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56: expected unsigned short [unsigned] [usertype] val drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56: got restricted __le16 [usertype] BA_timeout_value Signed-off-by: David Decotigny <ddecotig@gmail.com> --- drivers/staging/rtl8723au/core/rtw_mlme_ext.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/rtl8723au/core/rtw_mlme_ext.c b/drivers/staging/rtl8723au/core/rtw_mlme_ext.c index 7c3b5dd..142f214 100644 --- a/drivers/staging/rtl8723au/core/rtw_mlme_ext.c +++ b/drivers/staging/rtl8723au/core/rtw_mlme_ext.c @@ -3906,8 +3906,8 @@ void issue_action_BA23a(struct rtw_adapter *padapter, put_unaligned_le16(BA_para_set, &mgmt->u.action.u.addba_resp.capab); - put_unaligned_le16(pmlmeinfo->ADDBA_req.BA_timeout_value, - &mgmt->u.action.u.addba_resp.timeout); + mgmt->u.action.u.addba_resp.timeout + = pmlmeinfo->ADDBA_req.BA_timeout_value; pattrib->pktlen += 8; break; -- 2.2.0.rc0.207.ga3a616c -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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[PATCH v2 0/2] staging: rtl8723au: core: endianness issues David Decotigny <ddecotig@gmail.com> - 2015-06-07 02:40 +0200
[PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion David Decotigny <ddecotig@gmail.com> - 2015-06-07 02:40 +0200
[PATCH v2 1/2] staging: rtl8723au: core: avoid bitwise arithmetic with forced endianness David Decotigny <ddecotig@gmail.com> - 2015-06-07 03:00 +0200
Re: [PATCH v2 1/2] staging: rtl8723au: core: avoid bitwise arithmetic with forced endianness David Decotigny <ddecotig@gmail.com> - 2015-06-08 02:40 +0200
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