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Re: [PATCH v2 1/2] staging: rtl8723au: core: avoid bitwise arithmetic with forced endianness

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This was introduced by kernel bulk commit 5e93f3520 "staging: r8723au:
Add source files for new driver - part 1", initially from github
according to commit description. On github, this traces back to
another bulk commit: 2896bda04353 "Add new files in core directory",
which is the 1st version of the driver. Not sure where to find the
parent repos.

PS: sorry for the incorrect To/Cc, going to resend to more appropriate
recipients.

On Sun, Jun 7, 2015 at 4:20 AM, Dan Carpenter <dan.carpenter@oracle.com> wrote:
> You're CC'ing all the lustre people on this by mistake.
>
> Can we find which patch introduced this bug, and add a Fixes: tag and
> CC whoever introduced it?
>
> Please, resend with the correct CC list.
>
> regards,
> dan carpenter
>
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[PATCH v2 0/2] staging: rtl8723au: core: endianness issues David Decotigny <ddecotig@gmail.com> - 2015-06-07 02:40 +0200
  [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion David Decotigny <ddecotig@gmail.com> - 2015-06-07 02:40 +0200
  [PATCH v2 1/2] staging: rtl8723au: core: avoid bitwise arithmetic with forced endianness David Decotigny <ddecotig@gmail.com> - 2015-06-07 03:00 +0200
    Re: [PATCH v2 1/2] staging: rtl8723au: core: avoid bitwise arithmetic  with forced endianness David Decotigny <ddecotig@gmail.com> - 2015-06-08 02:40 +0200

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