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Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations

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On Mon, 2015-08-17 at 14:19 -0700, Dave Hansen wrote:
> On 08/17/2015 01:44 PM, Tim Chen wrote:
> > @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
> >  #define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)
> >  #define cpu_has_topoext		boot_cpu_has(X86_FEATURE_TOPOEXT)
> >  #define cpu_has_bpext		boot_cpu_has(X86_FEATURE_BPEXT)
> > +#define cpu_has_sha_ni		boot_cpu_has(X86_FEATURE_SHA_NI)
> 
> I think we're trying not to add these cpu_has_* macros any more.  For
> MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly.
> 
> In the patch description, it might also be nice to remind folks that
> this will feature will also show up as "sha_ni" in /proc/cpuinfo.

Okay, in that case, I've modified the patch to below:

Tim

--->8---

Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions
 implementations
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, H. Peter Anvin <hpa@zytor.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>, Chandramouli Narayanan <mouli@linux.intel.com>, x86@kernel.org, linux-kernel@vger.kernel.org

The Intel Secure Hash Algorithm Extensions are designed to improve the performance
of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit.

This will allow the feature to be shown as sha_ni in the /proc/cpuinfo.

The SHA extension programming guide is found in chapter 8 of the Intel
Architecture Instruction Set Extensions Programming reference:
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf

Signed-off-by: Chandramouli Narayanan <mouli@linux.intel.com>
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606f..a94f83d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -239,6 +239,7 @@
 #define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */
 #define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */
 #define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA_NI	( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
 
 /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
 #define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */
-- 
1.8.3.1



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Thread

[PATCH] sha: Enable cpuid check for Intel SHA extensions  implementations Tim Chen <tim.c.chen@linux.intel.com> - 2015-08-17 22:50 +0200
  Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations Dave Hansen <dave.hansen@intel.com> - 2015-08-17 23:20 +0200
    Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions  implementations Tim Chen <tim.c.chen@linux.intel.com> - 2015-08-18 00:40 +0200
      Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions  implementations Thomas Gleixner <tglx@linutronix.de> - 2015-08-18 18:50 +0200
        Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions  implementations Tim Chen <tim.c.chen@linux.intel.com> - 2015-08-19 19:00 +0200

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