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Groups > linux.kernel > #1182614
| From | YH Huang <yh.huang@mediatek.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v5 1/3] dt-bindings: pwm: add MediaTek display PWM bindings |
| Date | 2015-07-13 11:10 +0200 |
| Message-ID | <pLHUm-3aG-11@gated-at.bofh.it> (permalink) |
| References | <pLHUl-3aG-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Document the device-tree binding of MediatTek display PWM.
The PWM has one channel to control the backlight brightness for display.
It supports MT8173 and MT6595.
Signed-off-by: YH Huang <yh.huang@mediatek.com>
---
.../devicetree/bindings/pwm/pwm-mtk-disp.txt | 29 ++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
new file mode 100644
index 0000000..aac29dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
@@ -0,0 +1,29 @@
+MediaTek display PWM controller
+
+Required properties:
+ - compatible: should be "mediatek,<name>-disp-pwm":
+ - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
+ - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
+ - reg: physical base address and length of the controller's registers.
+ - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
+ the cell format.
+ - clocks: phandle and clock specifier of the PWM reference clock.
+ - clock-names: must contain the following:
+ - "main": clock used to generate PWM signals.
+ - "mm": sync signals from the modules of mmsys.
+ - pinctrl-names: Must contain a "default" entry.
+ - pinctrl-0: One property must exist for each entry in pinctrl-names.
+ See pinctrl/pinctrl-bindings.txt for details of the property values.
+
+Example:
+ pwm0: pwm@1401e000 {
+ compatible = "mediatek,mt8173-disp-pwm",
+ "mediatek,mt6595-disp-pwm";
+ reg = <0 0x1401e000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_DISP_PWM026M>,
+ <&mmsys CLK_MM_DISP_PWM0MM>;
+ clock-names = "main", "mm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_pwm0_pins>;
+ };
--
1.8.1.1.dirty
--
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[PATCH v5 0/3] Add MediaTek display PWM driver YH Huang <yh.huang@mediatek.com> - 2015-07-13 11:10 +0200
[PATCH v5 1/3] dt-bindings: pwm: add MediaTek display PWM bindings YH Huang <yh.huang@mediatek.com> - 2015-07-13 11:10 +0200
Re: [PATCH v5 1/3] dt-bindings: pwm: add MediaTek display PWM bindings Daniel Kurtz <djkurtz@chromium.org> - 2015-07-13 12:30 +0200
[PATCH v5 3/3] arm64: dts: mt8173: add MT8173 display PWM driver support node YH Huang <yh.huang@mediatek.com> - 2015-07-13 11:10 +0200
[PATCH v5 2/3] pwm: add MediaTek display PWM driver support YH Huang <yh.huang@mediatek.com> - 2015-07-13 11:10 +0200
Re: [PATCH v5 2/3] pwm: add MediaTek display PWM driver support Daniel Kurtz <djkurtz@chromium.org> - 2015-07-13 12:30 +0200
Re: [PATCH v5 2/3] pwm: add MediaTek display PWM driver support Daniel Kurtz <djkurtz@chromium.org> - 2015-07-16 17:30 +0200
Re: [PATCH v5 2/3] pwm: add MediaTek display PWM driver support YH Huang <yh.huang@mediatek.com> - 2015-07-16 18:50 +0200
Re: [PATCH v5 2/3] pwm: add MediaTek display PWM driver support Daniel Kurtz <djkurtz@chromium.org> - 2015-07-16 19:20 +0200
Re: [PATCH v5 2/3] pwm: add MediaTek display PWM driver support YH Huang <yh.huang@mediatek.com> - 2015-07-17 08:40 +0200
Re: [PATCH v5 2/3] pwm: add MediaTek display PWM driver support Daniel Kurtz <djkurtz@chromium.org> - 2015-07-17 09:10 +0200
Re: [PATCH v5 2/3] pwm: add MediaTek display PWM driver support YH Huang <yh.huang@mediatek.com> - 2015-07-17 10:10 +0200
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