Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1181393
| Path | csiph.com!aioe.org!bofh.it!news.nic.it!robomod |
|---|---|
| From | James Liao <jamesjj.liao@mediatek.com> |
| Newsgroups | linux.kernel |
| Subject | [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings |
| Date | Fri, 10 Jul 2015 10:50:02 +0200 |
| Message-ID | <pKCam-3EX-31@gated-at.bofh.it> (permalink) |
| References | <pKC0G-3Bu-25@gated-at.bofh.it> |
| X-Original-To | Matthias Brugger <matthias.bgg@gmail.com>, Mike Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, Heiko Stubner <heiko@sntech.de> |
| X-Listener-Flag | 11101 |
| X-Mailer | git-send-email 1.8.1.1.dirty |
| MIME-Version | 1.0 |
| Content-Type | text/plain |
| X-Mtk | N |
| Sender | robomod@news.nic.it |
| List-ID | <linux-kernel.vger.kernel.org> |
| X-Mailing-List | linux-kernel@vger.kernel.org |
| Approved | robomod@news.nic.it |
| Lines | 32 |
| Organization | linux.* mail to news gateway |
| X-Original-Cc | <srv_heupstream@mediatek.com>, Daniel Kurtz <djkurtz@chromium.org>, Ricky Liang <jcliang@chromium.org>, Rob Herring <robh+dt@kernel.org>, Sascha Hauer <kernel@pengutronix.de>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, James Liao <jamesjj.liao@mediatek.com> |
| X-Original-Date | Fri, 10 Jul 2015 16:39:33 +0800 |
| X-Original-Message-ID | <1436517574-17895-3-git-send-email-jamesjj.liao@mediatek.com> |
| X-Original-References | <1436517574-17895-1-git-send-email-jamesjj.liao@mediatek.com> |
| X-Original-Sender | linux-kernel-owner@vger.kernel.org |
| Xref | aioe.org linux.kernel:1181393 |
Show key headers only | View raw
Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
drivers/clk/mediatek/clk-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 68af518..0e3f4ef 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -144,9 +144,9 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
if (freq > pll->data->fmax)
freq = pll->data->fmax;
- for (val = 0; val < 4; val++) {
+ for (val = 0; val < 5; val++) {
*postdiv = 1 << val;
- if (freq * *postdiv >= fmin)
+ if ((u64)freq * *postdiv >= fmin)
break;
}
--
1.8.1.1.dirty
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH v3 0/3] Fixes for MT8173 PLLs James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:40 +0200 [PATCH v3 3/3] clk: mediatek: Add MT8173 MMPLL change rate support James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:50 +0200 [PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:50 +0200 [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:50 +0200 Re: [PATCH v3 0/3] Fixes for MT8173 PLLs Sascha Hauer <s.hauer@pengutronix.de> - 2015-07-13 07:50 +0200
csiph-web