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[PATCH v3 0/3] Fixes for MT8173 PLLs

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Title changed. Previous title is "Add MT8173 MMPLL change rate support"
and can be found in [1].

This patchset contains some fixes for changing rate of PLLs, especially
for MMPLL.

The first 2 patches are common fixes for PLLs, and the last patch is a
fix to support MT8173 MMPLL changing rate because its frequency setting
is different from other PLLs.

changes since v2:
- Rebase to 4.2-rc1.
- Split fixes of PLL setting calculation to a separeted patch.

changes since v1:
- Add a separated patch for mtk_pll_set_rate_regs().
- Use a structure array to describe a div_table.
- Limit max frequency to div_table[0].
- Minor changes such as static and comments.

[1] https://lkml.org/lkml/2015/7/8/265

James Liao (3):
  clk: mediatek: Fix PLL registers setting flow
  clk: mediatek: Fix calculation of PLL rate settings
  clk: mediatek: Add MT8173 MMPLL change rate support

 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
 3 files changed, 54 insertions(+), 15 deletions(-)

--
1.8.1.1.dirty

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[PATCH v3 0/3] Fixes for MT8173 PLLs James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:40 +0200
  [PATCH v3 3/3] clk: mediatek: Add MT8173 MMPLL change rate support James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:50 +0200
  [PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:50 +0200
  [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings James Liao <jamesjj.liao@mediatek.com> - 2015-07-10 10:50 +0200
  Re: [PATCH v3 0/3] Fixes for MT8173 PLLs Sascha Hauer <s.hauer@pengutronix.de> - 2015-07-13 07:50 +0200

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