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About VISC architecture

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  About VISC architecture Ramine <ramine@1.1> - 2014-11-15 16:45 -0800
    Re: About VISC architecture Ramine <ramine@1.1> - 2014-11-15 17:04 -0800

#4926 — About VISC architecture

Hello,


I have took a look at the following link about the performance
of the VISC architecture of Soft Machines...

http://www.bit-tech.net/news/hardware/2014/10/24/soft-machines-visc/1

Notice that they are saying that Soft Machines says that:

"The result, the team behind the technology claims, is a boost in 
instructions per cycle of 3-4 times compared to existing technologies 
resulting in a 2-4 times boost in performance per watt on both single- 
and multi-threaded applications.:"


Am i misunderstanding here? cause from what i know about parallel 
programming, that scalability is dependant also on the serial part
of the Amdahl equation, so in a "more" memory bound application it can
not scale to 2-4 times, so how can they say that in general there VISC 
architecture boosts performance by 2-4 times ? is it a marketing move ?




Thank you,
Amine Moulay Ramdane.

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#4927

Hello,


Read here on the following link , they have come to the same conclusion 
as me, cause in a "more" memory bound parallel application ,
the serial part of the Amdahl's law will be bigger because
multicore machines serializes the access to the memory bus,
so it will not scale and you will even have a retrograde throughput
because of contention on the memory bus , and that's the way it is with 
multicores machines and i think that's not different with VISC 
architecture of Soft Machines.


Read here please:


https://share.sandia.gov/news/resources/news_releases/more-chip-cores-can-mean-slower-supercomputing-sandia-simulation-shows/#.VGf2o4odhK8



Thank you,
Amine Moulay Ramdane.

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