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Groups > comp.programming > #4927
| From | Ramine <ramine@1.1> |
|---|---|
| Newsgroups | comp.programming |
| Subject | Re: About VISC architecture |
| Date | 2014-11-15 17:04 -0800 |
| Organization | A noiseless patient Spider |
| Message-ID | <m48ij5$ejo$2@dont-email.me> (permalink) |
| References | <m48hg1$aos$2@dont-email.me> |
Hello, Read here on the following link , they have come to the same conclusion as me, cause in a "more" memory bound parallel application , the serial part of the Amdahl's law will be bigger because multicore machines serializes the access to the memory bus, so it will not scale and you will even have a retrograde throughput because of contention on the memory bus , and that's the way it is with multicores machines and i think that's not different with VISC architecture of Soft Machines. Read here please: https://share.sandia.gov/news/resources/news_releases/more-chip-cores-can-mean-slower-supercomputing-sandia-simulation-shows/#.VGf2o4odhK8 Thank you, Amine Moulay Ramdane.
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About VISC architecture Ramine <ramine@1.1> - 2014-11-15 16:45 -0800 Re: About VISC architecture Ramine <ramine@1.1> - 2014-11-15 17:04 -0800
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