Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > comp.programming > #5171
| Path | csiph.com!v102.xanadu-bbs.net!xanadu-bbs.net!feeder.erje.net!eu.feeder.erje.net!eternal-september.org!feeder.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail |
|---|---|
| From | Mark Carroll <mtbc@bcs.org> |
| Newsgroups | comp.programming |
| Subject | Re: [hardware] memory bandwidth limitations (IMPORTANT) |
| Date | Sat, 31 Jan 2015 12:16:14 +0000 |
| Organization | none |
| Lines | 33 |
| Message-ID | <87zj8zcfht.fsf@ixod.org> (permalink) |
| References | <7922e2a8-e5a5-4b99-873e-5a4979505ca6@googlegroups.com> |
| Mime-Version | 1.0 |
| Content-Type | text/plain; charset=us-ascii |
| Injection-Info | mx02.eternal-september.org; posting-host="1b3e5cba9e4d07a53741e6f3d1717925"; logging-data="3512"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+i3alGSDZoRqN0Q78tXVUP" |
| User-Agent | Gnus/5.13 (Gnus v5.13) Emacs/23.4 (gnu/linux) |
| Cancel-Lock | sha1:fC22xQKBlCUgDRq7DQdiJxuA2ks= sha1:Cv06EhK7TZyitd0yBjZUClmOwgE= |
| Xref | csiph.com comp.programming:5171 |
Show key headers only | View raw
fir <profesor.fir@gmail.com> writes: > So the question is WHY it cannot be speeded up, canot this value of this > 1-lvl cache to cpu throughput (in both read and write) be increased? > what is real technical reason that it stays fixed and not improve I'd be surprised if it hadn't been improving, but I'd guess that we have three main technical limitations for general CPU design: * As you start using low power in microscopically tiny wiring you start running into quantum effects such as tunnelling. * It takes energy to change the voltages on the wires. The faster you do this, the more energy you use per second, so the hotter the chip gets. So, you run into thermal issues as power dissipates as heat. * When voltage changes are fast enough, you also run into high-frequency analog issues, such as inductance with the changing magnetic fields inducing current in nearby wiring. With regard to the cache issue, I'd also wonder if, in terms of moving data around between sections of the chip, such as between cache and computation, even with multi-layer stacked circuits there are also physical space limits regarding wiring the buses in and out of everywhere, and, with logic gates on the path in the cicuit (to route or whatever), there may well be propagation delays in the signal that are limiting at high computation speeds. I'd be interested to be corrected by somebody who knows rather more than I about modern CPU design; after all, the last hardware course I took was last century. -- Mark
Back to comp.programming | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[hardware] memory bandwidth limitations (IMPORTANT) fir <profesor.fir@gmail.com> - 2015-01-31 03:37 -0800
Re: [hardware] memory bandwidth limitations (IMPORTANT) Mark Carroll <mtbc@bcs.org> - 2015-01-31 12:16 +0000
Re: [hardware] memory bandwidth limitations (IMPORTANT) fir <profesor.fir@gmail.com> - 2015-01-31 06:03 -0800
csiph-web