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[hardware] memory bandwidth limitations (IMPORTANT)

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for me it seem the most crucial thing in todays hardware related to optymistation:

what if we can do arithmetic in 8-channel simds one step etc faster and faster, whan it is all limited by the memory bandwidth which is all in the range of reading 1 integer or float on 1 nanosecond

i saw many talks on how cpu is faster 
etc but it just seem that the overal speed is not so much dependant on cpu
this is dependant on memory bandwidth
i mean the time in which memory is
transfered form ram to cpu (this is probably 1-level cache to cpu transfer time; many people say how cache 9cache misses) are important, they also seem not important to me as my codes i observe nearly always fits the cache and i do not see any cache misses; it is just always limited by this cached movs
time (whose as i said are on the level 
1 int/ns)

So the question is WHY it cannot be speeded up, canot this value of this
1-lvl cache to cpu throughput (in both read and write) be increased? what is real technical reason that it stays fixed and not improve (this seem to me be probably both not maybe raw ram speed dependant, cpu arithmetic dependant, 
cache speed dependant - it seem to be just dependant on the 1-level cache to cpu stream; why it cannot be for example simd-like paralelised like arithmetic
is paralelised?

Hope the question is understandable

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[hardware] memory bandwidth limitations (IMPORTANT) fir <profesor.fir@gmail.com> - 2015-01-31 03:37 -0800
  Re: [hardware] memory bandwidth limitations (IMPORTANT) Mark Carroll <mtbc@bcs.org> - 2015-01-31 12:16 +0000
    Re: [hardware] memory bandwidth limitations (IMPORTANT) fir <profesor.fir@gmail.com> - 2015-01-31 06:03 -0800

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