Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > comp.programming.threads > #2682
| From | Ramine <ramine@1.1> |
|---|---|
| Newsgroups | comp.programming.threads |
| Subject | Re: About VISC architecture |
| Date | 2014-11-15 17:04 -0800 |
| Organization | A noiseless patient Spider |
| Message-ID | <m48ijd$ejo$3@dont-email.me> (permalink) |
| References | <m48hgf$aos$3@dont-email.me> |
Hello, Read here on the following link , they have come to the same conclusion as me, cause in a "more" memory bound parallel application , the serial part of the Amdahl's law will be bigger because multicore machines serializes the access to the memory bus, so it will not scale and you will even have a retrograde throughput because of contention on the memory bus , and that's the way it is with multicores machines and i think that's not different with VISC architecture of Soft Machines. Read here please: https://share.sandia.gov/news/resources/news_releases/more-chip-cores-can-mean-slower-supercomputing-sandia-simulation-shows/#.VGf2o4odhK8 Thank you, Amine Moulay Ramdane.
Back to comp.programming.threads | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
About VISC architecture Ramine <ramine@1.1> - 2014-11-15 16:45 -0800
Re: About VISC architecture Ramine <ramine@1.1> - 2014-11-15 17:04 -0800
Re: About VISC architecture Tom <mail2devnull@web.de> - 2014-11-24 15:23 +0100
csiph-web