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Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits.

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  Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits. Ian Martin Ajzenszmidt <iajzenszmi@gmail.com> - 2011-08-16 11:38 -0700
    Re: Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits. MitchAlsup <MitchAlsup@aol.com> - 2011-08-16 12:13 -0700
      Re: Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits. Ian Martin Ajzenszmidt <iajzenszmi@gmail.com> - 2011-08-16 13:53 -0700
        Re: Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits. "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-08-16 18:11 -0700
          Re: Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits. Robert Wessel <robertwessel2@yahoo.com> - 2011-08-16 20:38 -0500
            Re: Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits. "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-08-16 20:50 -0700
              Re: Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits. Robert Wessel <robertwessel2@yahoo.com> - 2011-08-16 23:43 -0500

#3047 — Binary switching logic circuits versus rotary switching 1 to n position switching logic circuits.

Binary switching logic circuits versus rotary switching 1 to n
position
switching logic circuits. Anybody interested in implementing rotary
switching 1
to n position logic, where n is any number from 1 to infinity, in
hardware software or firmware? Interesting possibilities lie ahead.
Rotary switching logic is more versatile than binary switching logic.
Memory and logic rotary based?

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#3050

The reason that binary "took over" in logic design is that it has the largest signal to noise tollerance of any logic family. This translates into vanishingly low error rates and highest possible speed/power product.

1-bit inverter 60 GHz
4-bit flash converter 7 GHz
8-bit A/D 200 MHz
14-bit A/D 16 MHz
20-bit A/D 2 MHz  (only reaches 18.3 bits of precision)

Notice a pattern?

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#3053

On Aug 17, 5:13 am, MitchAlsup <MitchAl...@aol.com> wrote:
> The reason that binary "took over" in logic design is that it has the largest signal to noise tollerance of any logic family. This translates into vanishingly low error rates and highest possible speed/power product.
>
> 1-bit inverter 60 GHz
> 4-bit flash converter 7 GHz
> 8-bit A/D 200 MHz
> 14-bit A/D 16 MHz
> 20-bit A/D 2 MHz  (only reaches 18.3 bits of precision)
>
> Notice a pattern?

Based on the following Wikipedia article, and its Literature
citations, use 2 to n possible value logic, where n is a number from 1
to infinity. Lower electricity consumption.

http://en.wikipedia.org/wiki/Ternary_computer


Ternary computer
From Wikipedia, the free encyclopedia


Setun ternary computer designed by Nikolay Brusentsov in the Soviet
Union.
A ternary computer (also called trinary computer) is a computer that
uses ternary logic (three possible values) instead of the more common
binary logic (two possible values) in its calculations.
Contents [hide]
1 History
2 Balanced ternary
3 The future
4 Ternary computers in popular culture
5 Literature
6 See also
7 References
8 External links
[edit]History

One of the earliest calculating machines, built by Thomas Fowler
entirely from wood in 1840, was a ternary computer. The only modern,
electronic ternary computer Setun was built in the late 1950s in the
Soviet Union at the Moscow State University by Nikolay Brusentsov, and
it had notable advantages over the binary computers which eventually
replaced it (such as lower electricity consumption and lower
production cost). In 1970 Brusentsov built an enhanced version of the
computer, which he called Setun-70.
[edit]Balanced ternary

Main article: Balanced ternary
Ternary computing is commonly implemented in terms of balanced
ternary, which uses the three digits -1, 0, and +1. The negative value
of any balanced ternary digit can be obtained by replacing every +
with a – and vice versa. It is easy to subtract a number by inverting
the + and – digits and then using normal addition. Balanced ternary
can express negative values as easily as positive ones, without the
need for a leading negative sign as with decimal numbers. These
advantages make some calculations more efficient in ternary than
binary.
"I often reflect that had the Ternary instead of the binary Notation
been adopted in the Infancy of Society, machines something like the
present would long ere this have been common, as the transition from
mental to mechanical calculation would have been so very obvious and
simple". (Fowler, 1840)
[edit]The future

With the advent of mass-produced binary components for computers,
ternary computers have diminished to a small footnote in the history
of computing. However, ternary logic's elegance and efficiency is
predicted by Donald Knuth to bring them back into development in the
future.[1] Possible ways on how this can happen is by the combination
of an optical computer with the ternary logic system.[2] A ternary
computer using fiber optics could use dark as 0 and two orthogonal
polarizations of light as 1 and -1. This future potential has also
been remarked by certain companies as Hypres which is actively engaged
in ternary computing. IBM also reports infrequently on ternary
computing topics (in its papers), but it is not actively engaged in
it.
The Josephson junction has been proposed as a balanced ternary memory
cell, using circulating superconducting currents, either clockwise,
counterclockwise, or off. "The advantages of the proposed memory
circuit are capability of high speed computation, low power
consumption and very simple construction with less number of elements
due to the ternary operation."[3]
In 2009, a ternary quantum computer was proposed which thus uses
qutrits rather than qubits. When the number of basic states of quantum
element is d, it is called qudit.[4]
[edit]Ternary computers in popular culture

In Robert A. Heinlein's novel Time Enough for Love, the sentient
computers of Secundus, the planet on which part of the framing story
is set, including Minerva, use an unbalanced ternary system. Minerva,
in reporting a calculation result, says "three hundred forty one
thousand six hundred forty... the original ternary readout is unit
pair pair comma unit nil nil comma unit pair pair comma unit nil nil
point nil" (Chapter Variations on a Theme III: Domestic Problems,
Berkley books 19th printing [1982] page 99)
[edit]Literature

Hunger, Francis: SETUN. An Inquiry into the Soviet Ternary Computer.
Institut für Buchkunst Leipzig, 2008, ISBN 3-932865-48-0 (English,
German)
[edit]See also

Ternary numeral system
Balanced ternary
Setun
Ternary logic
Ternac
Ternary flip-flap-flop[5]
Ternary SRAM
[edit]References

^ D.E. Knuth, The Art of Computer Programming - Volume 2:
Seminumerical Algorithms, pp. 190-192. Addison-Wesley, 2nd ed., 1980.
ISBN 0-201-03822-6.
^ Ternary Optical Computer
^ doi:10.1109/ISMVL.1998.679270
^ Qudits
^ Ternary "flip-flap-flop"
[edit]External links

Development of ternary computers at Moscow State University
The ternary calculating machine of Thomas Fowler
Ternary Optical computer
Trinary.cc - logic gates used to build a ternary computer
Ternary Computing Testbed 3-Trit Computer ArchitecturePDF (6.6 MB)
Computer Model of Ternary 3-Trit Computer Architecture TCA2 in 3-Bit
System of Ternary Logic Elements
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#3064

On 8/16/2011 1:53 PM, Ian Martin Ajzenszmidt wrote:
> On Aug 17, 5:13 am, MitchAlsup<MitchAl...@aol.com>  wrote:
>> The reason that binary "took over" in logic design is that it has the largest signal to noise tollerance of any logic family. This translates into vanishingly low error rates and highest possible speed/power product.
>>
>> 1-bit inverter 60 GHz
>> 4-bit flash converter 7 GHz
>> 8-bit A/D 200 MHz
>> 14-bit A/D 16 MHz
>> 20-bit A/D 2 MHz  (only reaches 18.3 bits of precision)
>>
>> Notice a pattern?
>
> Based on the following Wikipedia article, and its Literature
> citations, use 2 to n possible value logic, where n is a number from 1
> to infinity. Lower electricity consumption.
>
> http://en.wikipedia.org/wiki/Ternary_computer

Yeah?  So?

It's still an issue of noise.

If you have a circuit technology that is extremely low noise, go for 
multilevel.

Note that flash uses multiple signal levels per bitcell - although it is 
quickly converted into binary.



>
> Main article: Balanced ternary
> Ternary computing is commonly implemented in terms of balanced
> ternary, which uses the three digits -1, 0, and +1. The negative value
> of any balanced ternary digit can be obtained by replacing every +
> with a – and vice versa. It is easy to subtract a number by inverting
> the + and – digits and then using normal addition. Balanced ternary
> can express negative values as easily as positive ones, without the
> need for a leading negative sign as with decimal numbers. These
> advantages make some calculations more efficient in ternary than
> binary.

By the way: I suspect that what you (and wikipedia) call ternary is, in 
the computer arithmetic community[*], usually called "signed binary".

The distinction binary versus ternary is made according to the base.

E.g. if you have a number whose digits are
     {d_i} = {dn, d_n-1, ... d2, d1, d0}

then it is a binary notation if the value is

D = sum d_i * 2**i

and it is a ternary notation if the value is

D = sum d_i * 3**i


There is no restriction that the digit set be only two values, {0,1}, in 
binary.

It is quite common to have digit sets of {-1,0,1} in binary,  also 
{-1,0,1,2}, etc.   Sometimes {-1,1}, with no zero, for specialized 
applications.

---

[*] At least, this is what I was taught to call it, by Robertson, the R 
in SRT division.   And I am fairly certain that it is current in most.

I am surprised that Knuth calls it ternary.  I will ask him about that 
in November.

---

I suppose that we could say that the digit set is binary or ternary, 
while the base is 2.

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#3065

On Tue, 16 Aug 2011 18:11:33 -0700, "Andy \"Krazy\" Glew"
<andy@SPAM.comp-arch.net> wrote:

>On 8/16/2011 1:53 PM, Ian Martin Ajzenszmidt wrote:
>> On Aug 17, 5:13 am, MitchAlsup<MitchAl...@aol.com>  wrote:
>>> The reason that binary "took over" in logic design is that it has the largest signal to noise tollerance of any logic family. This translates into vanishingly low error rates and highest possible speed/power product.
>>>
>>> 1-bit inverter 60 GHz
>>> 4-bit flash converter 7 GHz
>>> 8-bit A/D 200 MHz
>>> 14-bit A/D 16 MHz
>>> 20-bit A/D 2 MHz  (only reaches 18.3 bits of precision)
>>>
>>> Notice a pattern?
>>
>> Based on the following Wikipedia article, and its Literature
>> citations, use 2 to n possible value logic, where n is a number from 1
>> to infinity. Lower electricity consumption.
>>
>> http://en.wikipedia.org/wiki/Ternary_computer
>
>Yeah?  So?
>
>It's still an issue of noise.
>
>If you have a circuit technology that is extremely low noise, go for 
>multilevel.
>
>Note that flash uses multiple signal levels per bitcell - although it is 
>quickly converted into binary.


And MLC flash would be pretty unusable without error correction.

Something I've wondered about for years is that I've never heard of
anyone doing anything other than four or eight level MLC flash.  Given
that essentially all MLC flash goes into disk-like products with
sector-size (or bigger) accesses, doing an odd (non-power-of-two)
number of levels is perfectly plausible, since you can even that out
over many bits (and the left over can be very, very small).  You could
obviously have a lot more room to tweak or gradually evolve your
process.

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#3066

On 8/16/2011 6:38 PM, Robert Wessel wrote:
> On Tue, 16 Aug 2011 18:11:33 -0700, "Andy \"Krazy\" Glew"
> <andy@SPAM.comp-arch.net>  wrote:
>
>> On 8/16/2011 1:53 PM, Ian Martin Ajzenszmidt wrote:
>>> On Aug 17, 5:13 am, MitchAlsup<MitchAl...@aol.com>   wrote:
>>>> The reason that binary "took over" in logic design is that it has the largest signal to noise tollerance of any logic family. This translates into vanishingly low error rates and highest possible speed/power product.
>>>>
>>>> 1-bit inverter 60 GHz
>>>> 4-bit flash converter 7 GHz
>>>> 8-bit A/D 200 MHz
>>>> 14-bit A/D 16 MHz
>>>> 20-bit A/D 2 MHz  (only reaches 18.3 bits of precision)
>>>>
>>>> Notice a pattern?
>>>
>>> Based on the following Wikipedia article, and its Literature
>>> citations, use 2 to n possible value logic, where n is a number from 1
>>> to infinity. Lower electricity consumption.
>>>
>>> http://en.wikipedia.org/wiki/Ternary_computer
>>
>> Yeah?  So?
>>
>> It's still an issue of noise.
>>
>> If you have a circuit technology that is extremely low noise, go for
>> multilevel.
>>
>> Note that flash uses multiple signal levels per bitcell - although it is
>> quickly converted into binary.
>
>
> And MLC flash would be pretty unusable without error correction.
>
> Something I've wondered about for years is that I've never heard of
> anyone doing anything other than four or eight level MLC flash.  Given
> that essentially all MLC flash goes into disk-like products with
> sector-size (or bigger) accesses, doing an odd (non-power-of-two)
> number of levels is perfectly plausible, since you can even that out
> over many bits (and the left over can be very, very small).  You could
> obviously have a lot more room to tweak or gradually evolve your
> process.

A friend of mine who designs flash disks / SSDs told me that when you 
have, say, 4 level MLC flash, it is

NOT 2 bits from the same disk block encoded in the same physical storage 
cell

BUT 2 separate bits, from 2 separate disk blocks, encoded in the same 
physical storage cell.

He said that the products he designed could not write any of the 4 
levels all at the same time.

Instead, he said that you can only write to half of the levels at a 
time. I did not quite follow why, although I might guess that it is 
related to error correction, and that you are always doing RMWs.

If this is (still) true, then it might explain why tri-level is hard: 
you would not just be writing ceil( NBitsPerBlock/3 ) storage cells with 
arbitrary ternary values.

With zeroing being a special operation.

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#3067

On Tue, 16 Aug 2011 20:50:22 -0700, "Andy \"Krazy\" Glew"
<andy@SPAM.comp-arch.net> wrote:

>On 8/16/2011 6:38 PM, Robert Wessel wrote:
>> On Tue, 16 Aug 2011 18:11:33 -0700, "Andy \"Krazy\" Glew"
>> <andy@SPAM.comp-arch.net>  wrote:
>>
>>> On 8/16/2011 1:53 PM, Ian Martin Ajzenszmidt wrote:
>>>> On Aug 17, 5:13 am, MitchAlsup<MitchAl...@aol.com>   wrote:
>>>>> The reason that binary "took over" in logic design is that it has the largest signal to noise tollerance of any logic family. This translates into vanishingly low error rates and highest possible speed/power product.
>>>>>
>>>>> 1-bit inverter 60 GHz
>>>>> 4-bit flash converter 7 GHz
>>>>> 8-bit A/D 200 MHz
>>>>> 14-bit A/D 16 MHz
>>>>> 20-bit A/D 2 MHz  (only reaches 18.3 bits of precision)
>>>>>
>>>>> Notice a pattern?
>>>>
>>>> Based on the following Wikipedia article, and its Literature
>>>> citations, use 2 to n possible value logic, where n is a number from 1
>>>> to infinity. Lower electricity consumption.
>>>>
>>>> http://en.wikipedia.org/wiki/Ternary_computer
>>>
>>> Yeah?  So?
>>>
>>> It's still an issue of noise.
>>>
>>> If you have a circuit technology that is extremely low noise, go for
>>> multilevel.
>>>
>>> Note that flash uses multiple signal levels per bitcell - although it is
>>> quickly converted into binary.
>>
>>
>> And MLC flash would be pretty unusable without error correction.
>>
>> Something I've wondered about for years is that I've never heard of
>> anyone doing anything other than four or eight level MLC flash.  Given
>> that essentially all MLC flash goes into disk-like products with
>> sector-size (or bigger) accesses, doing an odd (non-power-of-two)
>> number of levels is perfectly plausible, since you can even that out
>> over many bits (and the left over can be very, very small).  You could
>> obviously have a lot more room to tweak or gradually evolve your
>> process.
>
>A friend of mine who designs flash disks / SSDs told me that when you 
>have, say, 4 level MLC flash, it is
>
>NOT 2 bits from the same disk block encoded in the same physical storage 
>cell
>
>BUT 2 separate bits, from 2 separate disk blocks, encoded in the same 
>physical storage cell.
>
>He said that the products he designed could not write any of the 4 
>levels all at the same time.
>
>Instead, he said that you can only write to half of the levels at a 
>time. I did not quite follow why, although I might guess that it is 
>related to error correction, and that you are always doing RMWs.
>
>If this is (still) true, then it might explain why tri-level is hard: 
>you would not just be writing ceil( NBitsPerBlock/3 ) storage cells with 
>arbitrary ternary values.
>
>With zeroing being a special operation.


I have some trouble believing this - it's a single charge stored in a
single floating gate, written through a single mechanism.  Perhaps if
there was something funky in the write mechanism that could only put
one of two or three power levels on the write line (so on a 8 level
MLC, one write would "write" 0 or 4*N J to the cell, the second 0 or
2*N J to the cell, and the third 0 or1*N J).  But that would be a
limitation of the drivers on the write circuitry, not something really
inherent in the storage cell.  And it would obviously be trivial (if
carrying a bit of a performance penalty - although the actual write
time isn't really the major performance bottleneck on most flash) to
write two half blocks to the same region (assuming a four level cell)
in two cycles.  And multiple write cycles would still work with "odd"
numbers of levels - you could write to a five level cell with
combinations of 4N, 2N and 1N writes (obviously omitting three of the
possible combinations).

Perhaps they were storing the blocks in such a way to improve error
correction - it would spread out the data over move cells, reducing
the impact of a single failed cell on any stored block.  IOW, If a
single block used all three bits in a cell, the cell failing would
require three bits to be handled by the FEC mechanism - spread it out,
and you end up with three blocks needing a single bit of FEC. (In
reality the number of bits to be corrected would certainly be larger
than a single cell's worth).  Depending on the probability
distribution of errors, that could be an advantage.  Blocks are
sometimes interleaved that way on communications links for similar
reasons (it reduces the impact of an error burst on a given block).

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