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Re: What are the various alternate uses for the PC's LSB ?

Message-ID <4DCF1AEE.4050101@SPAM.comp-arch.net> (permalink)
Date 2011-05-14 17:14 -0700
From "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net>
Organization comp-arch.net
Newsgroups comp.arch
Subject Re: What are the various alternate uses for the PC's LSB ?
References <9226d60e-0c97-4863-97ab-1fc568a7bb46@glegroupsg2000goo.googlegroups.com> <iqhv4i$bg8$1@speranza.aioe.org> <4DCCA664.9070207@SPAM.comp-arch.net> <nqev98-qvt2.ln1@ntp6.tmsw.no> <iqjjk2$ldo$1@dont-email.me>

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On 5/13/2011 8:44 AM, Stephen Fuld wrote:
> On 5/13/2011 3:47 AM, Terje Mathisen wrote:

> Not having to handle this is the advantage of test and set. It could
> relatively easily be implemented entirely within the memory chip itself.
> However, at the cost of that elegance, perhaps a reasonable compromise
> would be to handle the addition within the memory controller chip (or
> part of chip) instead of the RAM chips. This still avoids the need for
> bus locks/snoops. It would cost a second transfer at the RAM chips
> themselves, but since many/most RAM to controller interfaces are 64 bits
> wide, it makes the overflow problem small enough that you might be able
> to not implement anything special for it.

Long ago ago I described, on this newsgroup, how to generalize any RMW, 
and perform it locally in cache if possible, else in the L2, ... else in 
the memory controller, else in ...

Basically, instead of read/write and the ability to lock a cache line or 
delay snoops, you define an operation RMW(address,size,operation,operand)
at every level of the cache hierarchy that you care too.
I.e. ideally every level.


At the N-th level
RMW(address,size,operation,operand)
    if( !properly_aliged(address,size) ) ...
    if( address is in M or E state ) {
         tmp := read(address,size)
         tmp op= operand
         write(address,size)
    }
    else {
         send to the N+1st level
    }


you can do this all the way out to the memory chip, assuming all 
intervening levels support.

you get the benefit of local caching for synchronization variables if 
they are private to your cache, remote fetch and op if not.


etc.

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Re: What are the various alternate uses for the PC's LSB ? "Paul A. Clayton" <paaronclayton@gmail.com> - 2011-05-12 08:49 -0700
  Re: What are the various alternate uses for the PC's LSB ? whygee <yg@yg.yg> - 2011-05-13 02:01 +0200
    Re: What are the various alternate uses for the PC's LSB ? "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-05-12 20:32 -0700
      Re: What are the various alternate uses for the PC's LSB ? Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-05-13 12:47 +0200
        Re: What are the various alternate uses for the PC's LSB ? Stephen Fuld <SFuld@alumni.cmu.edu.invalid> - 2011-05-13 08:44 -0700
          Re: What are the various alternate uses for the PC's LSB ? Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-05-13 19:53 +0200
            Re: What are the various alternate uses for the PC's LSB ? Stephen Fuld <SFuld@alumni.cmu.edu.invalid> - 2011-05-13 11:36 -0700
              Re: What are the various alternate uses for the PC's LSB ? Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-05-13 22:26 +0200
            Re: What are the various alternate uses for the PC's LSB ? "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-05-14 17:17 -0700
              Re: What are the various alternate uses for the PC's LSB ? Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-05-16 14:22 +0200
                Re: What are the various alternate uses for the PC's LSB ? "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-05-16 07:38 -0700
          Re: What are the various alternate uses for the PC's LSB ? "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-05-14 17:14 -0700
      Re: What are the various alternate uses for the PC's LSB ? rpw3@rpw3.org (Rob Warnock) - 2011-05-13 07:45 -0500

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