Freescale 9S12 Shared I/Os

From	Randy Yates <yates@digitalsignallabs.com>
Newsgroups	comp.arch.embedded
Subject	Freescale 9S12 Shared I/Os
Organization	Digital Signal Labs
Date	2013-08-19 09:51 -0400
Message-ID	<877gfhrdoi.fsf@digitalsignallabs.com> (permalink)

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Hi,

I have a requirement to use bits 6 and 7 of Port J on a Freescale
MC9S12DG128CPVE device as an IIC peripheral. It is not clear to me
whether or not, in addition to simply "turning on" the peripheral
via the IBEN bit in the IIC Bus Control Register (IBCR), manual
configuration of bits 6 and 7 on port J is required.

Specifically, I have the following questions on the configuration
for these bits:

  1. Do I need to do something to select these bits for the
  IIC module as opposed to GPIO, CAN or whatever other purposes
  these bits can be used for?

  2. Do I need to set the DDRJ (data direction register)?

  3. Do I need to set the RDRJ (reduced drive register)?

  4. Do I need to set the PERJ (pull device enable register)?

  5. Do I need to set the PPSJ (polarity select register)?

  6. Do I need to set the PIFJ (interrupt flag register)?

  7. Do I need to set the PPSJ (polarity select register)?

As I understand the PIM Block guide and the information about
"precedences" for this port, simply setting the IBEN bit in the IBCR is
all I need to do, provided no other peripheral for the port (e.g., CAN4)
is enabled. Is this correct?
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com

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Freescale 9S12 Shared I/Os Randy Yates <yates@digitalsignallabs.com> - 2013-08-19 09:51 -0400

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