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delta-sigma ADC in FPGA

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Usually when I ask about delta-sigma ADCs in FPGAs the comments are along the lines of "terrible idea", "can't mix analog and digital", etc.  I'm very much not convinced.  

I think people have a view of the ADC as being a device with very balanced specs, resolution, SNR, etc.  In this application we need significantly more resolution than we do accuracy.  The measurement is differential pressure across an orifice in a gas flow rate sensor.  The conversion curve for pressure to flow rate has a square root.  This makes the measurement much more sensitive to resolution at the low end.  

The signal is the human breath with a very low frequency content.  The fundamental is 0.5 Hz maximum with various harmonic content.  Our sample rate is 200 Hz.  

The analog input circuit approximates the delta-sigma model with resistors from the input and the feedback summing currents to an integrating capacitor.  The capacitor voltage is compared to a Vref (very accurately 1/2 Vcco) with a differential input on the FPGA.  The Vcco for this I/O bank is isolated from other supplies and no other signals are on this power rail.  

The processing of the captured signal is a simple counter, accumulate and dump.  Many texts on this design show the use of a second stage of filtering which I believe is mostly present to shape the frequency response of the CIC filter.  This is not useful in this application. 

In a post elsewhere someone commented that a boxcar filter (the accumulate and dump) is not equivalent to a CIC filter, but without explaining.  I can't see the distinction other than the CIC offers configurations that the boxcar filter doesn't.  But certainly the boxcar filter gives identical results to a configuration of CIC filter. 

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  Rick C.

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delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-15 19:27 -0800
  Re: delta-sigma ADC in FPGA  Yes there are times when the (difference/sum) ratio is a life-saver.For example, when the sum is varying FAST over a wide range. navaide <navaide@gmail.com> - 2020-11-16 18:31 -0800
  Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-18 15:07 -0800
    Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-18 20:15 -0800
      Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-19 11:44 -0800
        Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-20 02:01 -0800
          Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-20 13:52 -0800
            Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-20 18:00 -0800
              Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-20 22:02 -0800
                Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-21 01:58 -0800
  Re: delta-sigma ADC in FPGA Rafael Deliano <rafael_deliano@arcor.de> - 2020-11-22 10:24 +0100
    Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-22 15:10 -0800

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