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Re: delta-sigma ADC in FPGA

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I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics.  The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail.  The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.  

An alternative to this is to use a level shifter to provide a full 5V swing.  The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value.  But it appears the ultimate limitation becomes the symmetry of the buffer switching.  Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor.  My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.  

I've found a very few parts that list symmetrical limits on the prop delays.  I assume that means they will track better than other devices.  It will be interesting to test these ADC. 

-- 

Rick C.

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delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-15 19:27 -0800
  Re: delta-sigma ADC in FPGA  Yes there are times when the (difference/sum) ratio is a life-saver.For example, when the sum is varying FAST over a wide range. navaide <navaide@gmail.com> - 2020-11-16 18:31 -0800
  Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-18 15:07 -0800
    Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-18 20:15 -0800
      Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-19 11:44 -0800
        Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-20 02:01 -0800
          Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-20 13:52 -0800
            Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-20 18:00 -0800
              Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-20 22:02 -0800
                Re: delta-sigma ADC in FPGA boB <boB@K7IQ.com> - 2020-11-21 01:58 -0800
  Re: delta-sigma ADC in FPGA Rafael Deliano <rafael_deliano@arcor.de> - 2020-11-22 10:24 +0100
    Re: delta-sigma ADC in FPGA Rick C <gnuarm.deletethisbit@gmail.com> - 2020-11-22 15:10 -0800

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