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Re: Volatile keyword

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On Mon, 12 Dec 2011, markspace wrote:

> On 12/12/2011 4:51 AM, raphfrk@gmail.com wrote:
>
>> Effectively, does the CPU lock the entire 64-bits for the long when 
>> doing the write update, and so other threads either seen the updated 
>> value or the old value?
>
> I don't like the word "lock" here because it implies something that probably 
> isn't happening.  I think that volatile, even for long and double, is 
> specified to be much lighter weight than a lock.
>
> The spec that Lew referred to says they are "atomic" and doesn't mention 
> "lock."  I think of them that way, myself, in addition to "light weight" as 
> opposed to the more heavy actual lock.
>
> volatile long === light weight & atomic.
>
> (=== here meant to mean "defined to be.")

I don't think it's *defined to be* lightweight. A sadistic JVM implementor 
could make it heavyweight without violating the spec. However, it is 
indeed *defined in such a way as that it can be implemented as* 
lightweight, which is what i think you were getting at.

I would imagine that on the x86, volatile writes to longs are implemented 
by issuing the store instruction with the LOCK prefix, which prevents 
other cores from using the bus until the instruction completes - it's a 
sort of micro-lock, much lighter-weight than a monitor entry. Although 
here is an interesting thread:

http://stackoverflow.com/questions/78277/how-to-guarantee-64-bit-writes-are-atomic

which indicates that my imagination is completely wrong! Suggestions are 
that (a) aligned 64-bit stores are atomic on Pentiums and later anyway, 
and that (b) you can use FISTP to do an intrinsically atomic 64-bit store 
(although that's a FPU instruction - such is the x86 way).

On the PowerPC, if there isn't an atomic 64-bit store, i think you can use 
the load linked/store conditional instructions: LL the second word, do a 
normal store to the first word, then SC to the second word. Oh no, hang 
on, you can still get a race on the first word. Oh well, i suspect that 
the PowerPC has an atomic 64-bit store anyway.

I have no idea what you'd do on a SPARC. I can't think of any other 
interesting chips for JVMs. ARM, maybe? Even less idea there! Ooh, or the 
ShenWei SW-3? Apparently that uses the MIPS instruction set.

tom

-- 
Politically there are two options: Socialism or barbarism. -- King
Aarthoor

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Volatile keyword "raphfrk@gmail.com" <raphfrk@gmail.com> - 2011-12-12 04:51 -0800
  Re: Volatile keyword Andreas Leitgeb <avl@gamma.logic.tuwien.ac.at> - 2011-12-12 14:31 +0000
    Re: Volatile keyword "raphfrk@gmail.com" <raphfrk@gmail.com> - 2011-12-12 06:52 -0800
  Re: Volatile keyword Lew <lewbloch@gmail.com> - 2011-12-12 06:34 -0800
  Re: Volatile keyword markspace <-@.> - 2011-12-12 10:00 -0800
    Re: Volatile keyword Tom Anderson <twic@urchin.earth.li> - 2011-12-12 18:41 +0000
      Re: Volatile keyword Patricia Shanahan <pats@acm.org> - 2011-12-12 11:43 -0800
    Re: Volatile keyword Roedy Green <see_website@mindprod.com.invalid> - 2011-12-12 11:15 -0800
      Re: Volatile keyword Robert Klemme <shortcutter@googlemail.com> - 2011-12-13 08:37 +0100
        Re: Volatile keyword Peter Duniho <NpOeStPeAdM@NnOwSlPiAnMk.com> - 2011-12-12 23:54 -0800
          Re: Volatile keyword Robert Klemme <shortcutter@googlemail.com> - 2011-12-14 19:39 +0100
            Re: Volatile keyword Daniel Pitts <newsgroup.nospam@virtualinfinity.net> - 2011-12-14 10:59 -0800
            Re: Volatile keyword Patricia Shanahan <pats@acm.org> - 2011-12-14 11:00 -0800
              Re: Volatile keyword Robert Klemme <shortcutter@googlemail.com> - 2011-12-14 22:35 +0100
  Re: Volatile keyword Roedy Green <see_website@mindprod.com.invalid> - 2011-12-12 10:55 -0800

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