Re: Constant Stack Canaries

From	Robert Finch <robfi680@gmail.com>
Newsgroups	comp.arch
Subject	Re: Constant Stack Canaries
Date	2025-04-06 15:01 -0400
Organization	A noiseless patient Spider
Message-ID	<vsuj2d$1lvvs$1@dont-email.me> (permalink)
References	(9 earlier) <vsq91i$18k1q$1@dont-email.me> <760b3834d1202502f5f63e52b51cfdc8@www.novabbs.org> <kGeIP.467285$d51.395138@fx46.iad> <vss913$3b1ga$1@dont-email.me> <G5wIP.1525956$eNx6.852360@fx14.iad>

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On 2025-04-06 10:21 a.m., Scott Lurndal wrote:
> Robert Finch <robfi680@gmail.com> writes:
>> On 2025-04-05 2:31 p.m., Scott Lurndal wrote:
>>> mitchalsup@aol.com (MitchAlsup1) writes:
>>>> On Sat, 5 Apr 2025 3:45:51 +0000, Robert Finch wrote:
>>>>
>>>
>>>>> Would not writing to the GuestOs VAS and the application VAS be the
>>>>> result of separate system calls? Or does the hypervisor take over for
>>>>> the GuestOS?
>>>>
>>>> Application has a 64-bit VAS
>>>> GusetOS has a 64-bit VAS
>>>> HyprVisor has a 64-bit VAS
>>>> and so does
>>>> Securte has a 64-bit VAS
>>>>
>>>> So, we are in HV and we need to write to guestOS and to Application
>>>> but we have only 1-bit of distinction.
>>>
>>> On ARM64, when the HV needs to write to guest user VA or guest PA,
>>> the SMMU provides an interface the processor can use to translate
>>> the guest VA or Guest PA to the corresponding system physical address.
>>> Of course, there is a race if the guest OS changes the underlying
>>> translation tables during the upcall to the hypervisor or secure
>>> monitor, although that would be a bug in the guest were it so to do,
>>> since the guest explicitly requested the action from the higher
>>> privilege level (e.g. HV).
>>>
>>> Arm does have a set of load/store "user" instructions that translate
>>> addresses using the unprivileged (application) translation tables.  There's
>>> also a processor state bit (UAO - User Access Override) that can
>>> be set to force those instructions to use the permissions associated
>>> with the current processor privilege level.
>>>
>>> Note that there is a push by all vendors to include support
>>> for guest 'privacy', such that the hypervisor has no direct
>>> access to memory owned by the guest, or where the the guest
>>> memory is encrypted using a key the hypervisor or secure monitor
>>> don't have access to.
>>>
>> Okay,
>>
>> I was interpreting RISCV specs wrong. They have three bits dedicated to
>> this. 1 is an on/off and the other two are the mode to use. I am left
>> wondering how it is determined which mode to use. If the hypervisor is
>> passed a pointer to a VAS variable in a register, how does it know that
>> the pointer is for the supervisor or the user/app?
> 
> When the exception (in this case an upcall to a more privileged
> regime) occurs, the saved state register/stack word should contain the prior
> privilege level.   The hypervisor will know from that whether
> the upcall was from the guest OS or a guest Application.
> 
Yes, Q+ works that way, I think RISCV does as well. Q+ stacks the PC and 
SR on an internal stack which is basically a shift register. The TOS is 
visible as a CR. The mode is state saved in the SR. Interrupts and 
exceptions do not have to store the state in memory. The far end of the 
stack is hard coded to do a reset if the stack underflows.

> Note that on ARM, there are restrictions on upcalls to
> more privileged regimes - generally a particular regime
> can only upcall the next higher privileged regime, so
> the user app can only upcall the GuestOS,  the guest OS can only
> upcall the HV and the HV is the only regime that can
> upcall the secure monitor.
> 
Allows two directional virtualization I think. Q+ has all exceptions and 
interrupts going to the secure monitor, which can then delegate it back 
to a lower level.

>> It's why I assumed it
>> found the mode from the stack. Those two select bits have to set
>> somehow. It seems like extra code to access the right address space.'
> 
> I haven't spent much time with RISC-V, but surely the processor
> has a state register that stores the current mode, and which
> must be preserved over exceptions/upcalls, which would require
> that they be recorded in an exception syndrome register for
> restoration when the upcall returns.
>

Thread

Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-03-30 08:16 -0400
  Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-03-30 12:47 -0500
    Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-03-30 20:14 +0000
      Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-03-30 21:26 -0400
      Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-03-31 01:34 -0500
      Re: Constant Stack Canaries Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-03-31 09:04 -0700
        Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-03-31 12:17 -0500
          Re: Constant Stack Canaries Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-03-31 10:57 -0700
          Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-03-31 18:07 +0000
            Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-03-31 13:56 -0500
              Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-03-31 20:52 +0000
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-01 00:58 -0400
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-01 18:51 +0000
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-01 18:06 -0400
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-01 23:24 +0000
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-01 20:07 -0400
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-02 01:47 +0000
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-04 21:07 +0000
                Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-04-01 16:21 -0500
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-01 18:19 -0400
                Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-04-01 23:04 -0500
                Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-04-01 14:34 -0500
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-01 23:21 +0000
                Re: Constant Stack Canaries Stefan Monnier <monnier@iro.umontreal.ca> - 2025-04-01 22:55 -0400
                Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-04-01 23:19 -0500
                Re: Constant Stack Canaries Stefan Monnier <monnier@iro.umontreal.ca> - 2025-04-03 10:09 -0400
                Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-04-03 12:22 -0500
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-03 23:49 -0400
                Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-04-04 12:41 -0500
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-04 21:13 +0000
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-04 23:45 -0400
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-05 16:37 +0000
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-05 18:31 +0000
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-05 17:57 -0400
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-05 23:11 +0000
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-06 14:21 +0000
                Re: Constant Stack Canaries Robert Finch <robfi680@gmail.com> - 2025-04-06 15:01 -0400
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-07 14:04 +0000
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-05 23:06 +0000
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-06 14:32 +0000
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-07 00:51 +0000
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-07 14:09 +0000
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-09 00:23 +0000
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-15 00:43 +0000
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-15 14:02 +0000
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-15 20:46 +0000
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-16 14:07 +0000
                Re: Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-16 21:13 +0000
                Virtualization layers (was: Constant Stack Canaries) Stefan Monnier <monnier@iro.umontreal.ca> - 2025-04-16 17:48 -0400
                Re: Virtualization layers mitchalsup@aol.com (MitchAlsup1) - 2025-04-16 22:12 +0000
                Re: Virtualization layers (was: Constant Stack Canaries) scott@slp53.sl.home (Scott Lurndal) - 2025-04-17 00:49 +0000
                Re: Constant Stack Canaries Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-04-16 15:26 -0700
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-17 00:57 +0000
                Re: virtualization, Constant Stack Canaries John Levine <johnl@taugh.com> - 2025-04-17 01:04 +0000
                Re: virtualization, Constant Stack Canaries Stefan Monnier <monnier@iro.umontreal.ca> - 2025-04-16 21:07 -0400
                Re: virtualization, Constant Stack Canaries Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2025-04-16 23:30 -0700
                Re: virtualization, Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-17 13:32 +0000
                Re: virtualization, Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-17 18:22 +0000
                Re: virtualization, Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-17 20:10 +0000
                Re: virtualization, Constant Stack Canaries mitchalsup@aol.com (MitchAlsup1) - 2025-04-17 21:45 +0000
                Re: Constant Stack Canaries scott@slp53.sl.home (Scott Lurndal) - 2025-04-17 00:47 +0000
                Re: Constant Stack Canaries BGB <cr88192@gmail.com> - 2025-04-02 00:43 -0500

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