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Re: Proof that DD correctly simulated by HH provides the correct halt status criteria

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On 6/9/24 8:49 AM, olcott wrote:
> On 6/9/2024 2:23 AM, Mikko wrote:
>> On 2024-06-08 12:27:09 +0000, olcott said:
>>
>>> On 6/8/2024 12:53 AM, Mikko wrote:
>>>> On 2024-06-07 21:48:57 +0000, olcott said:
>>>>
>>>>> *That no counter-example to the following exists proves that it is 
>>>>> true*
>>>>
>>>> Not wihout a proof that no counter-example exists.
>>>>
>>>
>>> I incorporate by reference
>>> (a) The x86 language
>>> (b) The notion of an x86 emulator
>>>
>>> (c) I provide this complete function
>>>
>>> void DDD(int (*x)())
>>> {
>>>    HH(x, x);
>>> }
>>>
>>> _DDD()
>>> [00001de2] 55         push ebp
>>> [00001de3] 8bec       mov ebp,esp
>>> [00001de5] 8b4508     mov eax,[ebp+08]
>>> [00001de8] 50         push eax         ; push DDD
>>> [00001de9] 8b4d08     mov ecx,[ebp+08]
>>> [00001dec] 51         push ecx         ; push DDD
>>> [00001ded] e890f5ffff call 00001382    ; call HH
>>> [00001df2] 83c408     add esp,+08
>>> [00001df5] 5d         pop ebp
>>> [00001df6] c3         ret
>>> Size in bytes:(0021) [00001df6]
>>>
>>> Then I state that No DDD correctly emulated by any
>>> x86 emulator H can possibly reach its own [00001df6]
>>> instruction.
>>>
>>> To anyone having this mandatory prerequisite knowledge
>>> (perhaps not you) every x86 emulation of DDD by any
>>> x86 emulator H continually repeats the first seven lines
>>> of DDD until it crashes due to out-of-memory error.
>>>
>>> Try and show that the above sequence is incorrect, you
>>> cannot because it is correct.
>>
>> OK. Tell us when you have a proof with that incorporated.
>>
> 
> That <is> a complete proof to anyone that has all of the mandatory 
> prerequisite knowledge.
> 
> The first seven steps of DDD correctly simulated by HH
> call HH(DDD,DDD) to repeat these first seven steps.

Nope. The HH that is simulating DD, should, by your definition continue 
simulating the code of HH as THAT OTHER HH simulates those same first 
seven steps.

The outer HH will never see its execution trace get back to the 
beginning of DD.


> 
> HH then simulates itself simulating DD until this second
> instance of DDD calls another HH(DDD,DDD) to repeat these
> first seven steps again.
> 
> New slave_stack at:103278
> Begin Local Halt Decider Simulation   Execution Trace Stored at:113280
>   machine   stack     stack     machine    assembly
>   address   address   data      code       language
>   ========  ========  ========  =========  =============
> [00001df3][0011326c][00113270] 55         push ebp
> [00001df4][0011326c][00113270] 8bec       mov ebp,esp
> [00001df6][0011326c][00113270] 8b4508     mov eax,[ebp+08]
> [00001df9][00113268][00001df3] 50         push eax        ; push DDD
> [00001dfa][00113268][00001df3] 8b4d08     mov ecx,[ebp+08]
> [00001dfd][00113264][00001df3] 51         push ecx        ; push DDD
> [00001dfe][00113260][00001e03] e830f5ffff call 00001333   ; call HH
> New slave_stack at:14dca0

ERROR ERROR ERROR

Your simulator is broken and does follow your rules,

Call 00001333 must be followed by the simulation of the instruction at 
00001333

Obviously you just don't understand how computers work, or are just a 
pathological liar.


> [00001df3][0015dc94][0015dc98] 55         push ebp
> [00001df4][0015dc94][0015dc98] 8bec       mov ebp,esp
> [00001df6][0015dc94][0015dc98] 8b4508     mov eax,[ebp+08]
> [00001df9][0015dc90][00001df3] 50         push eax        ; push DDD
> [00001dfa][0015dc90][00001df3] 8b4d08     mov ecx,[ebp+08]
> [00001dfd][0015dc8c][00001df3] 51         push ecx        ; push DD
> [00001dfe][0015dc88][00001e03] e830f5ffff call 00001333   ; call HH
> Infinite Recursion Detected Simulation Stopped
> 
> 

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Proof that DD correctly simulated by HH provides the correct halt status criteria olcott <polcott333@gmail.com> - 2024-06-07 16:48 -0500
  Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Python <python@invalid.org> - 2024-06-07 23:59 +0200
    Re: Proof that DD correctly simulated by HH provides the correct halt status criteria olcott <polcott333@gmail.com> - 2024-06-07 17:20 -0500
  Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Richard Damon <richard@damon-family.org> - 2024-06-07 18:15 -0400
  Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Mikko <mikko.levanto@iki.fi> - 2024-06-08 08:53 +0300
    Re: Proof that DD correctly simulated by HH provides the correct halt status criteria olcott <polcott333@gmail.com> - 2024-06-08 07:27 -0500
      Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Richard Damon <richard@damon-family.org> - 2024-06-08 09:01 -0400
      Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Mikko <mikko.levanto@iki.fi> - 2024-06-09 10:23 +0300
        Re: Proof that DD correctly simulated by HH provides the correct halt status criteria olcott <polcott333@gmail.com> - 2024-06-09 07:49 -0500
          Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Mikko <mikko.levanto@iki.fi> - 2024-06-09 18:01 +0300
          Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Richard Damon <richard@damon-family.org> - 2024-06-09 14:08 -0400
  Re: Proof that DD correctly simulated by HH provides the correct halt status criteria "Fred. Zwarts" <F.Zwarts@HetNet.nl> - 2024-06-08 10:46 +0200
    Re: Proof that DD correctly simulated by HH provides the correct halt status criteria olcott <polcott333@gmail.com> - 2024-06-08 07:23 -0500
      Re: Proof that DD correctly simulated by HH provides the correct halt status criteria Richard Damon <richard@damon-family.org> - 2024-06-08 09:02 -0400

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