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Groups > linux.kernel > #1693411
| From | Simon Xue <xxm@rock-chips.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH V2 3/4] ARM64: dts: rockchip: rk3368 add iommu nodes |
| Date | 2017-07-21 08:30 +0200 |
| Message-ID | <u5zBN-1do-27@gated-at.bofh.it> (permalink) |
| References | <u5zBM-1do-23@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Simon <xxm@rock-chips.com>
Add IEP/ISP/VOP/HEVC/VPU iommu nodes
Signed-off-by: Simon <xxm@rock-chips.com>
---
changes since V1:
- add rk-iommu,disable-reset-quirk for isp mmu to ignore the isp mmu
reset operation
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 49 ++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 6d5dc05..98cacc0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -724,6 +724,55 @@
status = "disabled";
};
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ #iommu-cells = <0>;
+ rk-iommu,disable-reset-quirk;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu@ff930300 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff930300 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hevc_mmu: iommu@ff9a0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0440 0x0 0x40>,
+ <0x0 0xff9a0480 0x0 0x40>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu", "vdpu_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
--
1.9.1
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[PATCH V2 1/4] ARM64: dts: rockchip: rk3328 add iommu nodes Simon Xue <xxm@rock-chips.com> - 2017-07-21 08:30 +0200 [PATCH V2 3/4] ARM64: dts: rockchip: rk3368 add iommu nodes Simon Xue <xxm@rock-chips.com> - 2017-07-21 08:30 +0200 [PATCH V2 2/4] ARM: dts: rockchip: rk322x add iommu nodes Simon Xue <xxm@rock-chips.com> - 2017-07-21 08:30 +0200 [PATCH V2 4/4] ARM64: dts: rockchip: rk3399 add iommu nodes Simon Xue <xxm@rock-chips.com> - 2017-07-21 08:30 +0200
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