SPI Quad Serial Flash: two "quad" modes?

From	pozz <pozzugno@gmail.com>
Newsgroups	comp.arch.embedded
Subject	SPI Quad Serial Flash: two "quad" modes?
Date	2023-04-04 22:57 +0200
Organization	A noiseless patient Spider
Message-ID	<u0i2vg$3idod$1@dont-email.me> (permalink)

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I'm studying datasheet of SST26VF080A. It's a SPI Quad Flash memory in 
standard 8 pin package.

I'm not sure I correctly understood the quad mode. It appears to me two 
quad modes are supported: SPI Quad mode (IOC=1 in Configuration 
Register) and SQI mode (after sending Enable Quad I/O command).

For example, after setting IOC bit in Configuration Register I can use 
SQOR command (SPI Quad Output Read) to output data from SIO[3:0] pins.

A similar behaviour can be obtained after enabling SQI mode (sending 
EQIO=Enable Quad I/O mode) and using High-Speed Read command (0x0B).

What is the difference? I think the difference is only in the data 
transmitted by the SPI master: opcode byte, address bytes and dummy 
bytes. In the first case, they are transmitted serially on a single 
signal (SI/SIO0); in SQI mode, they are transmitted serially on 4 
signals (SIO[3-0]). The behaviour on data transmitted by the serial 
Flash should be exactly the same: they are transmitted on the 4 signals 
SIO[3-0].

Is my understanding correct?

I think the penalty of the first Quad mode respect the SQI mode is very 
small.

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SPI Quad Serial Flash: two "quad" modes? pozz <pozzugno@gmail.com> - 2023-04-04 22:57 +0200
  Re: SPI Quad Serial Flash: two "quad" modes? Grant Edwards <invalid@invalid.invalid> - 2023-04-04 23:29 +0000
  Re: SPI Quad Serial Flash: two "quad" modes? David Brown <david.brown@hesbynett.no> - 2023-04-05 17:52 +0200
    Re: SPI Quad Serial Flash: two "quad" modes? pozz <pozzugno@gmail.com> - 2023-04-11 08:46 +0200
      Re: SPI Quad Serial Flash: two "quad" modes? David Brown <david.brown@hesbynett.no> - 2023-04-11 12:31 +0200
      Re: SPI Quad Serial Flash: two "quad" modes? Don Y <blockedofcourse@foo.invalid> - 2023-04-11 05:00 -0700

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