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[PATCH v6 1/4] fpga: add config complete timeout

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From: Alan Tull <atull@opensource.altera.com>

Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
---
 drivers/fpga/fpga-region.c    | 3 +++
 include/linux/fpga/fpga-mgr.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
index 2fe2a52..ae4c61a 100644
--- a/drivers/fpga/fpga-region.c
+++ b/drivers/fpga/fpga-region.c
@@ -385,6 +385,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
 	of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
 			     &info->disable_timeout_us);
 
+	of_property_read_u32(nd->overlay, "config-complete-timeout-us",
+			     &info->config_complete_timeout_us);
+
 	/* If FPGA was externally programmed, don't specify firmware */
 	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
 		pr_err("error: specified firmware and external-fpga-config");
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index e2ef94f..b4ac24c 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -77,11 +77,14 @@ enum fpga_mgr_states {
  * @flags: boolean flags as defined above
  * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
  * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
+ * @config_complete_timeout_us: maximum time for FPGA to switch to operating
+ *	   status in the write_complete op.
  */
 struct fpga_image_info {
 	u32 flags;
 	u32 enable_timeout_us;
 	u32 disable_timeout_us;
+	u32 config_complete_timeout_us;
 };
 
 /**
-- 
2.7.4

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[PATCH v6 0/4] Altera Partial Reconfiguration IP matthew.gerlach@linux.intel.com - 2017-03-21 22:10 +0100
  [PATCH v6 1/4] fpga: add config complete timeout matthew.gerlach@linux.intel.com - 2017-03-21 22:10 +0100
  [PATCH v6 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP. matthew.gerlach@linux.intel.com - 2017-03-21 22:10 +0100
    Re: [PATCH v6 3/4] fpga dt: bindings for Altera Partial  Reconfiguration IP. Alan Tull <delicious.quinoa@gmail.com> - 2017-03-22 16:30 +0100
  [PATCH v6 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. matthew.gerlach@linux.intel.com - 2017-03-21 22:10 +0100
    Re: [PATCH v6 2/4] fpga pr ip: Core driver support for Altera Partial  Reconfiguration IP. Alan Tull <delicious.quinoa@gmail.com> - 2017-03-22 16:40 +0100
  [PATCH v6 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP. matthew.gerlach@linux.intel.com - 2017-03-21 22:10 +0100
    Re: [PATCH v6 4/4] fpga pr ip: Platform driver for Altera Partial  Reconfiguration IP. Alan Tull <delicious.quinoa@gmail.com> - 2017-03-22 16:20 +0100

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